| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rcar-gen3: Mark RWDT clocks as critical | Ulrich Hecht | 2020-06-22 | 1 | -1/+1 |
| * | clk: renesas: r8a77980: Fix RPC-IF module clock's parent | Sergei Shtylyov | 2019-04-02 | 1 | -1/+1 |
| * | clk: renesas: r8a77980: Add RPC clocks | Sergei Shtylyov | 2019-02-05 | 1 | -0/+8 |
| * | clk: renesas: r8a77980: Add CMT clocks | Sergei Shtylyov | 2018-09-03 | 1 | -0/+4 |
| * | clk: renesas: r8a77980: Add RCLK for watchdog timer | Geert Uytterhoeven | 2018-08-27 | 1 | -0/+4 |
| * | clk: renesas: r8a77980: Add OSC predivider configuration and clock | Geert Uytterhoeven | 2018-08-27 | 1 | -11/+13 |
| * | clk: renesas: r8a77980: Correct parent clock of PCIEC0 | Geert Uytterhoeven | 2018-04-16 | 1 | -1/+1 |
| * | clk: renesas: cpg-mssr: add R8A77980 support | Sergei Shtylyov | 2018-02-20 | 1 | -0/+227 |
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