| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: r9a06g032: Fix UART34567 clock rate | Phil Edworthy | 2018-09-11 | 1 | -1/+2 |
| * | clk: renesas: Renesas R9A06G032 clock driver | Michel Pollet | 2018-06-25 | 1 | -0/+893 |
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