summaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas/rcar-gen3-cpg.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang2021-10-081-87/+2
* clk: renesas: rcar-gen3: Add boost support to Z clocksGeert Uytterhoeven2021-05-111-4/+20
* clk: renesas: rcar-gen3: Add custom clock for PLLsGeert Uytterhoeven2021-05-111-19/+128
* clk: renesas: rcar-gen3: Increase Z clock accuracyGeert Uytterhoeven2021-05-111-2/+2
* clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/Geert Uytterhoeven2021-05-111-1/+1
* clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()Geert Uytterhoeven2021-05-111-2/+1
* clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32Geert Uytterhoeven2021-05-111-1/+1
* clk: renesas: rcar-gen3: Update Z clock rate formula in commentsGeert Uytterhoeven2021-05-111-1/+2
* clk: renesas: Zero init clk_init_dataGeert Uytterhoeven2021-03-301-1/+1
* clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang2021-01-121-251/+1
* clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clockWolfram Sang2021-01-121-9/+10
* clk: renesas: r8a774c0: Add RPC clocksLad Prabhakar2020-12-101-0/+28
* clk: renesas: rcar-gen3: Remove stp_ck handling for SDHIWolfram Sang2020-10-261-26/+25
* clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov2019-12-201-2/+4
* clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()Geert Uytterhoeven2019-10-211-7/+12
* clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()Geert Uytterhoeven2019-10-211-8/+14
* clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()Geert Uytterhoeven2019-10-011-4/+8
* clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()Geert Uytterhoeven2019-10-011-14/+5
* clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()Geert Uytterhoeven2019-10-011-3/+3
* clk: renesas: rcar-gen3: Improve arithmetic divisionsGeert Uytterhoeven2019-10-011-2/+2
* clk: renesas: rcar-gen3: Remove unused variableStephen Boyd2019-04-111-1/+0
* clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara2019-04-041-16/+14
* clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman2019-04-021-2/+2
* clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman2019-04-021-1/+0
* clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman2019-04-021-11/+4
* clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara2019-04-021-9/+15
* clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()Geert Uytterhoeven2019-03-181-6/+6
* clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2019-02-051-0/+101
* clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov2019-01-251-0/+8
* clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov2019-01-251-18/+20
*-. Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd2018-12-141-22/+33
|\ \
| * | clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund2018-12-071-7/+26
| * | clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund2018-12-071-5/+5
| * | clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund2018-12-071-12/+4
| |/
* / clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd2018-12-101-1/+1
|/
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-191-9/+31
|\
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-271-6/+4
| * clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-271-3/+20
| * clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-271-0/+7
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-311-4/+1
|/
* clk: renesas: rcar-gen3: Always use readl()/writel()Geert Uytterhoeven2018-03-211-7/+7
* clk: renesas: rcar-gen3: Add Z2 clock divider supportTakeshi Kihara2018-02-121-6/+16
* clk: renesas: rcar-gen3: Add Z clock divider supportTakeshi Kihara2018-02-121-0/+133
* clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven2017-10-201-2/+11
* clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven2017-10-201-13/+50
* clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-201-1/+2
* clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-161-1/+19
* clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-161-0/+2
* clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang2017-07-191-26/+20
* clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang2017-07-191-2/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 08:48:23 +0100