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path: root/drivers/clk/renesas/rcar-gen3-cpg.c (follow)
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* clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-271-6/+4
| | | | | | | | | Make the existing support for selecting between clean and SSCG clocks using MD12 more generic, to allow using other mode pins for arbitrary clock selection. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-271-3/+20
| | | | | | | | Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-271-0/+7
| | | | | | | | | | | | | | Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Always use readl()/writel()Geert Uytterhoeven2018-03-211-7/+7
| | | | | | | | | | | | The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add Z2 clock divider supportTakeshi Kihara2018-02-121-6/+16
| | | | | | | | This patch adds Z2 clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Add Z clock divider supportTakeshi Kihara2018-02-121-0/+133
| | | | | | | | This patch adds Z clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven2017-10-201-2/+11
| | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register a notifier to save/restore the RCKCR register during system suspend/resume. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven2017-10-201-13/+50
| | | | | | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register a notifier to save/restore SDHI clock registers during system suspend/resume. This is implemented using the cpg_simple_notifier abstraction, which can be reused for others clocks that just need to save/restore a single register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-201-1/+2
| | | | | | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly losing clock configuration. Hence add a notifier chain that can be used by core clocks to save/restore clock state during system suspend/resume. The implementation of the actual clock state save/restore operations is clock-specific, and to be registered with the notifier chain in the SoC or family-specific cpg_mssr_info.cpg_clk_register() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-161-1/+19
| | | | | | | | | | | | | On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-161-0/+2
| | | | | | | | | | | On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang2017-07-191-26/+20
| | | | | | | | | Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang2017-07-191-2/+1
| | | | | | | 'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven2017-03-301-11/+27
| | | | | | | | | | | | Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. Add support for that, but retain the old behavior for R-Car H3 ES1.x and M3-W ES1.0 using a quirk. Inspired by a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
* clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0Geert Uytterhoeven2017-03-211-0/+24
| | | | | | | | | | Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and PLL4 clock frequencies are off by a factor of two. Inspired by a patch by Dien Pham in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Dien Pham <dien.pham.ry@renesas.com>
* clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven2017-03-211-1/+3
| | | | | | | | Pass the mode pin states from the SoC-specific CPG/MSSR driver to the R-Car Gen3 CPG driver core, as their state will be needed to make some core clock configuration decisions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge branch 'rcar-rst' into clk-renesas-for-v4.10Geert Uytterhoeven2016-11-021-17/+0
|\ | | | | | | soc: renesas: Add R-Car RST driver for obtaining mode pin state
| * clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()Geert Uytterhoeven2016-11-021-17/+0
| | | | | | | | | | | | | | | | | | All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* | clk: renesas: rcar-gen3-cpg: Always use readl()/writel()Geert Uytterhoeven2016-10-171-7/+7
|/ | | | | | | | | The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-061-0/+359
Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
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