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* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-1918-168/+1333
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
| * clk: renesas: r7s9210: Add SPI clocksChris Brandt2018-09-281-0/+3
| | | | | | | | | | | | | | | | Add RSPI clocks for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r7s9210: Move table update to separate functionChris Brandt2018-09-261-45/+50
| | | | | | | | | | | | | | Same functionality, just easier to read. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt2018-09-261-6/+26
| | | | | | | | | | | | | | | | The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the ostm module clocks to be registers early in boot. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add early clock supportChris Brandt2018-09-262-21/+89
| | | | | | | | | | | | | | | | | | Add support for SoCs that need to register core and module clocks early in order to use OF drivers that exclusively use macros such as TIMER_OF_DECLARE. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77970: Add TPU clockSergei Shtylyov2018-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven2018-09-251-2/+2
| | | | | | | | | | | | | | PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro2018-09-195-0/+299
| | | | | | | | | | | | | | | | | | | | | | | | Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and Software Reset support. Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.61, June 12, 2018)". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7743: Add r8a7744 supportBiju Das2018-09-193-2/+18
| | | | | | | | | | | | | | | | | | | | Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt2018-09-115-12/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov2018-09-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | The TMU clocks weren't present in the original R8A77970 patch by Daisuke Matsushita, they were added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov2018-09-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | Add the R8A77970 CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-09-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through 7 is UART34567. For UART012, we stop the clock driver from changing the clock rate. This is because the Synopsys UART driver simply sets the reference clock to 16x the baud rate, but doesn't check if the actual rate is within the required tolerance. The RZ/N1 clock divider can't provide this (we have to rely on the UART's internal divider to set the correct clock rate), so you end up with a clock rate that is way off what you wanted. In addition, since the clock is shared between multiple UARTs, you don't want the driver trying to change the clock rate as it may affect the other UARTs (which may not have been configured yet, so you don't know what baud rate they will use). Normally, the clock rate is set early on before Linux to some very high rate that supports all of the clock rates you want. This change stops the UART34567 clock rate from changing for the same reasons. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2018-09-032-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov2018-09-031-0/+4
| | | | | | | | | | | | | | | | | | | | Now that RCLK has been added by Geert, we can add the CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven2018-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to use I2C7 on R-Car E3: renesas-cpg-mssr e6150000.clock-controller: Cannot get module clock 1003: -2 i2c-rcar e6690000.i2c: failed to add to PM domain always-on: -2 i2c-rcar: probe of e6690000.i2c failed with error -2 Unlike other R-Car Gen3 SoCs, R-Car E3 has more than 7 I2C bus interfaces. Add the forgotten module clock for the 8th instance to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
| * clk: renesas: r8a77965: Add FDP clockHoan Nguyen An2018-08-281-0/+1
| | | | | | | | | | | | | | | | This patch adds FDP1-0 clock to the R8A77965 SoC. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-275-0/+336
| | | | | | | | | | | | | | | | | | | | | | | | Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: Hardware ((Rev. 0.61, June 12, 2018)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77965: Add SATA clockTakeshi Kihara2018-08-271-0/+1
| | | | | | | | | | | | | | | | | | | | This patch adds SATA clock to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [wsa: rebased to upstream base] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77980: Add RCLK for watchdog timerGeert Uytterhoeven2018-08-271-0/+4
| | | | | | | | | | | | | | | | On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip Oscillator using mode pin MD19. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-272-10/+13
| | | | | | | | | | | | | | | | | | Make the existing support for selecting between clean and SSCG clocks using MD12 more generic, to allow using other mode pins for arbitrary clock selection. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a77995: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a77990: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-272-4/+26
| | | | | | | | | | | | | | | | Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: cpg-mssr: Add support for fixed rate clocksGeert Uytterhoeven2018-08-272-0/+8
| | | | | | | | | | | | | | | | Add support for defining fixed rate clocks, to be used for on-chip oscillators. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a77980: Add OSC predivider configuration and clockGeert Uytterhoeven2018-08-271-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC clock. Hence augment the configuration structure with all documented predivider values. Add the OSC clock using the configured predivider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a77965: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car M3-N does not have the CPG_RCKCR register. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-N SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a7796: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car M3-W ES1.1. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-W SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a7795: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car H3 ES2.0. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car H3 SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-272-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven2018-08-273-3/+6
| | | | | | | | | | | | | | | | | | | | | | All other internal clock names have a period prepended. Hence rename the internal RCLK from "rint" to ".r", and move it to the section where all other internal clocks are defined. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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*-. | Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-nextStephen Boyd2018-10-1910-28/+28
|\ \| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
| * | clk: Convert to using %pOFn instead of device_node.nameRob Herring2018-08-3010-28/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: renesas: Convert to SPDX identifiersKuninori Morimoto2018-09-2921-89/+25
| | | | | | | | | | | | | | | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-318-32/+8
|/ | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-253-0/+900
| | | | | | | | | This provides a clock driver for the Renesas R09A06G032. This uses a structure derived from both the R-Car Gen2 driver as well as the renesas-cpg-mssr driver. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef2018-06-191-0/+1
| | | | | | | | This patch adds the clock used by the CryptoCell 630p instance in the SoC. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven2018-06-191-0/+1
| | | | | | | | | Add the CR core clock, which is used by the Secure Engine (SCEG). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-134-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kzalloc() function has a 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a * b, gfp) as well as handling cases of: kzalloc(a * b * c, gfp) with: kzalloc(array3_size(a, b, c), gfp) as it's slightly less ugly than: kzalloc_array(array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: kzalloc(4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ type TYPE; expression THING, E; @@ ( kzalloc( - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | kzalloc( - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression COUNT; typedef u8; typedef __u8; @@ ( kzalloc( - sizeof(u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(__u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(unsigned char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(__u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(char) * COUNT + COUNT , ...) | kzalloc( - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ identifier SIZE, COUNT; @@ - kzalloc + kcalloc ( - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( kzalloc( - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( kzalloc( - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ identifier STRIDE, SIZE, COUNT; @@ ( kzalloc( - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression E1, E2, E3; constant C1, C2, C3; @@ ( kzalloc(C1 * C2 * C3, ...) | kzalloc( - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | kzalloc( - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( kzalloc(sizeof(THING) * C2, ...) | kzalloc(sizeof(TYPE) * C2, ...) | kzalloc(C1 * C2 * C3, ...) | kzalloc(C1 * C2, ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - (E1) * E2 + E1, E2 , ...) | - kzalloc + kcalloc ( - (E1) * (E2) + E1, E2 , ...) | - kzalloc + kcalloc ( - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2018-06-0914-6/+578
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
| * clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda2018-05-095-0/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | Initial support for R-Car E3 (r8a77990), including core and module clocks. Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual: Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018". Inspried by patches by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rcar-gen2: Centralize quirks handlingGeert Uytterhoeven2018-04-161-4/+16
| | | | | | | | | | | | | | | | | | | | | | Introduce centralized quirks handling like on R-Car Gen3, and convert the RZ/G1C SD clock table handling over to it. This makes it easier to add more quirks later, if/when needed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
| * clk: renesas: r8a77980: Correct parent clock of PCIEC0Geert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of December 22, 2017, the parent clock of the PCIe module clock on R-Car V3H is S2D2. Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: r8a7794: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car E2, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
| * clk: renesas: r8a7792: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car V2H, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
| * clk: renesas: r8a7791/r8a7793: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car M2-W and M2-N, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
| * clk: renesas: r8a7745: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1E, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
| * clk: renesas: r8a7743: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1M, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
| * clk: renesas: cpg-mssr: Add r8a77470 supportBiju Das2018-04-166-0/+254
| | | | | | | | | | | | | | | | | | Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a77965: Add MSIOF controller clocksTakeshi Kihara2018-04-161-0/+4
| | | | | | | | | | | | | | | | This patch adds MSIOF{0,1,2,3} clocks to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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