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path: root/drivers/clk/renesas (follow)
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* Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2022-05-291-1/+39
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| * clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal2022-05-191-0/+5
| * clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal2022-05-191-1/+34
* | clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy2022-05-061-5/+9
* | clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-065-0/+181
* | clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2022-05-052-3/+17
* | clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-054-1/+16
* | clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-053-31/+19
* | clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-053-6/+12
* | clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-053-22/+19
* | clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven2022-05-051-1/+1
* | clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das2022-05-051-0/+6
* | clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das2022-05-051-0/+6
* | clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das2022-05-051-0/+9
* | clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das2022-05-051-0/+18
* | clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das2022-05-051-1/+16
* | clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das2022-05-051-1/+8
* | clk: renesas: r9a07g044: Add M4 Clock supportBiju Das2022-05-051-1/+18
* | clk: renesas: r9a07g044: Add M3 Clock supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add M1 clock supportBiju Das2022-05-051-1/+10
* | clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2022-05-052-0/+136
* | clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2022-05-052-0/+103
* | clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2022-05-052-0/+235
* | clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda2022-04-295-0/+231
* | clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda2022-04-294-16/+24
* | clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das2022-04-281-0/+10
* | clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das2022-04-281-0/+9
* | clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das2022-04-281-0/+5
* | clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das2022-04-281-0/+12
* | clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das2022-04-281-0/+20
* | clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das2022-04-281-0/+12
* | clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal2022-04-281-1/+1
* | clk: renesas: r8a779f0: Add UFS clockYoshihiro Shimoda2022-04-251-0/+1
* | clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das2022-04-131-0/+35
* | clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das2022-04-131-0/+10
* | clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das2022-04-131-0/+13
* | clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das2022-04-131-0/+5
* | clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-135-1/+171
* | clk: renesas: Move RPC core clocksGeert Uytterhoeven2022-04-1312-57/+51
* | clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven2022-04-131-1/+1
* | clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2022-04-112-1/+13
* | clk: renesas: r8a77990: Add RPC clocksGeert Uytterhoeven2022-04-111-0/+9
* | clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy2022-04-041-2/+0
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* clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven2022-02-221-0/+1
* clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven2022-02-221-0/+6
* clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven2022-02-221-0/+9
* clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven2022-02-221-1/+1
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-105-191/+250
* clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht2022-01-241-0/+1
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-04 13:39:51 +0100