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path: root/drivers/clk/renesas (follow)
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* clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven2022-02-221-0/+1
* clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven2022-02-221-0/+6
* clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven2022-02-221-0/+9
* clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven2022-02-221-1/+1
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-105-191/+250
* clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht2022-01-241-0/+1
* clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar2022-01-241-2/+2
* clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2022-01-242-0/+2
* clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda2022-01-241-0/+2
* clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das2021-12-081-0/+9
* clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2021-12-082-0/+10
* clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das2021-12-081-2/+2
* clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda2021-12-085-0/+196
* clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda2021-12-087-341/+437
* clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das2021-11-261-0/+3
* clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
* clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+14
* clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
* clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+13
* clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar2021-11-191-0/+9
* clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das2021-11-191-1/+10
* clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das2021-11-191-0/+2
* clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRSTWolfram Sang2021-11-191-12/+3
* clk: renesas: rcar-gen3: Switch to new SD clock handlingWolfram Sang2021-11-194-202/+32
* clk: renesas: r8a779a0: Add SDnH clock to V3UWolfram Sang2021-11-191-1/+10
* clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang2021-11-1910-32/+64
* clk: renesas: rcar-gen3: Add dummy SDnH clockWolfram Sang2021-11-194-0/+21
* clk: renesas: r9a07g044: Add OSTM clock and reset entriesBiju Das2021-11-151-0/+9
* clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macrosBiju Das2021-11-151-6/+6
* clk: renesas: r9a07g044: Add WDT clock and reset entriesBiju Das2021-11-151-0/+15
* clk: renesas: r9a07g044: Add clock and reset entry for SCI1Lad Prabhakar2021-11-151-0/+3
* clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven2021-11-152-0/+4
* clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov2021-10-153-0/+3
* clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das2021-10-082-0/+40
* clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das2021-10-082-0/+130
* clk: renesas: r8a779a0: Add RPC supportWolfram Sang2021-10-081-0/+32
* clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang2021-10-083-87/+92
* clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar2021-10-082-0/+21
* clk: renesas: r8a779a0: Add Z0 and Z1 clock supportGeert Uytterhoeven2021-09-281-0/+158
* clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das2021-09-241-0/+10
* clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das2021-09-242-1/+81
* clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das2021-09-242-1/+21
* clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das2021-09-242-0/+35
* clk: renesas: r8a779a0: Add TPU clockWolfram Sang2021-09-241-0/+1
* clk: renesas: rzg2l: Fix clk status functionBiju Das2021-09-241-1/+1
* clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das2021-09-241-0/+2
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-09-0210-26/+87
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| * clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven2021-08-131-3/+1
| * clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar2021-07-261-1/+2
| * clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar2021-07-191-0/+6
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 19:41:40 +0100