summaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: Zero init clk_init_dataGeert Uytterhoeven2021-03-308-16/+11
* clk: renesas: Couple of spelling fixesBhaskar Chowdhury2021-03-241-2/+2
* clk: renesas: r8a779a0: Add CMT clocksWolfram Sang2021-03-121-0/+4
* clk: renesas: r8a7795: Add TMU clocksNiklas Söderlund2021-03-121-0/+6
* clk: renesas: r8a779a0: Add TSC clockNiklas Söderlund2021-03-101-0/+1
* clk: renesas: r8a779a0: Add TMU clocksWolfram Sang2021-03-101-0/+6
* clk: renesas: r8a77965: Add DAB clockFabrizio Castro2021-03-081-0/+1
* clk: renesas: r8a77990: Add DAB clockFabrizio Castro2021-03-081-0/+1
* clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentationLee Jones2021-01-281-2/+2
* clk: renesas: r8a779a0: Add RAVB clocksWolfram Sang2021-01-251-0/+6
* clk: renesas: r8a779a0: Add I2C clocksWolfram Sang2021-01-251-0/+7
* clk: renesas: r8a779a0: Add SYS-DMAC clocksGeert Uytterhoeven2021-01-121-0/+2
* clk: renesas: r8a779a0: Add SDHI supportWolfram Sang2021-01-122-2/+16
* clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang2021-01-125-251/+309
* clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clockWolfram Sang2021-01-121-9/+10
* clk: renesas: r8a779a0: Add MSIOF clocksGeert Uytterhoeven2021-01-121-0/+6
* clk: renesas: r8a779a0: Add PFC/GPIO clocksGeert Uytterhoeven2021-01-121-0/+5
* clk: renesas: r8a779a0: Fix parent of CBFUSA clockGeert Uytterhoeven2021-01-071-1/+1
* clk: renesas: r8a779a0: Remove non-existent S2 clockGeert Uytterhoeven2021-01-071-1/+0
* clk: renesas: r8a779a0: Add HSCIF supportWolfram Sang2021-01-071-0/+4
* clk: renesas: r8a779a0: Add RWDT clocksWolfram Sang2020-12-281-0/+9
* clk: renesas: r8a779a0: Add VSPX clock supportKieran Bingham2020-12-281-0/+4
* clk: renesas: r8a779a0: Add VSPD clock supportKieran Bingham2020-12-281-0/+2
* clk: renesas: r8a779a0: Add FCPVD clock supportKieran Bingham2020-12-281-0/+2
* clk: renesas: r8a77995: Add TMU clocksNiklas Söderlund2020-12-281-0/+5
* clk: renesas: r8a77990: Add TMU clocksNiklas Söderlund2020-12-281-0/+5
* clk: renesas: r8a77965: Add TMU clocksNiklas Söderlund2020-12-281-0/+5
* clk: renesas: r8a7796: Add TMU clocksNiklas Söderlund2020-12-281-0/+5
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-219-33/+134
|\
| * clk: renesas: sh73a0: Stop using __raw_*() I/O accessorsGeert Uytterhoeven2020-12-101-1/+1
| * clk: renesas: r8a774c0: Add RPC clocksLad Prabhakar2020-12-103-0/+42
| * clk: renesas: r8a779a0: Fix R and OSC clocksGeert Uytterhoeven2020-12-101-3/+10
| * clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_privKrzysztof Kozlowski2020-12-101-1/+2
| * clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()Yejune Deng2020-12-101-1/+1
| * clk: renesas: r8a774b1: Add RPC clocksBiju Das2020-12-101-0/+8
| * clk: renesas: r8a774a1: Add RPC clocksBiju Das2020-12-101-0/+8
| * clk: renesas: r8a779a0: Add VIN clocksJacopo Mondi2020-12-101-0/+32
| * clk: renesas: r8a779a0: Add CSI4[0-3] clocksJacopo Mondi2020-12-101-0/+4
| * clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() staticGeert Uytterhoeven2020-12-101-1/+1
| * clk: renesas: rcar-gen3: Remove stp_ck handling for SDHIWolfram Sang2020-10-261-26/+25
* | clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven2020-12-071-1/+1
|/
* clk: renesas: rcar-gen3: Update description for RZ/G2Lad Prabhakar2020-09-171-1/+1
* clk: renesas: cpg-mssr: Add support for R-Car V3UYoshihiro Shimoda2020-09-175-1/+316
* clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_privYoshihiro Shimoda2020-09-171-35/+47
* clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flagYoshihiro Shimoda2020-09-173-19/+22
* clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)Lad Prabhakar2020-09-047-8/+8
* clk: renesas: r8a7742: Add clk entry for VSPRLad Prabhakar2020-09-041-1/+2
* clk: renesas: cpg-mssr: Add r8a774e1 supportMarian-Cristian Rotariu2020-07-135-0/+362
* clk: renesas: rzg2: Mark RWDT clocks as criticalUlrich Hecht2020-06-223-0/+3
* clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht2020-06-227-5/+7