| Commit message (Expand) | Author | Age | Files | Lines |
* | clk: renesas: r8a779[56]x: Add MLP clocks | Andrey Gusakov | 2021-10-15 | 3 | -0/+3 |
* | clk: renesas: r9a07g044: Add SDHI clock and reset entries | Biju Das | 2021-10-08 | 2 | -0/+40 |
* | clk: renesas: rzg2l: Add SDHI clk mux support | Biju Das | 2021-10-08 | 2 | -0/+130 |
* | clk: renesas: r8a779a0: Add RPC support | Wolfram Sang | 2021-10-08 | 1 | -0/+32 |
* | clk: renesas: cpg-lib: Move RPC clock registration to the library | Wolfram Sang | 2021-10-08 | 3 | -87/+92 |
* | clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co... | Lad Prabhakar | 2021-10-08 | 2 | -0/+21 |
* | clk: renesas: r8a779a0: Add Z0 and Z1 clock support | Geert Uytterhoeven | 2021-09-28 | 1 | -0/+158 |
* | clk: renesas: r9a07g044: Add GbEthernet clock/reset | Biju Das | 2021-09-24 | 1 | -0/+10 |
* | clk: renesas: rzg2l: Add support to handle coupled clocks | Biju Das | 2021-09-24 | 2 | -1/+81 |
* | clk: renesas: r9a07g044: Add ethernet clock sources | Biju Das | 2021-09-24 | 2 | -1/+21 |
* | clk: renesas: rzg2l: Add support to handle MUX clocks | Biju Das | 2021-09-24 | 2 | -0/+35 |
* | clk: renesas: r8a779a0: Add TPU clock | Wolfram Sang | 2021-09-24 | 1 | -0/+1 |
* | clk: renesas: rzg2l: Fix clk status function | Biju Das | 2021-09-24 | 1 | -1/+1 |
* | clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical | Biju Das | 2021-09-24 | 1 | -0/+2 |
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2021-09-02 | 10 | -26/+87 |
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| * | clk: renesas: Make CLK_R9A06G032 invisible | Geert Uytterhoeven | 2021-08-13 | 1 | -3/+1 |
| * | clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 | Lad Prabhakar | 2021-07-26 | 1 | -1/+2 |
| * | clk: renesas: r9a07g044: Add clock and reset entries for ADC | Lad Prabhakar | 2021-07-19 | 1 | -0/+6 |
| * | clk: renesas: r9a07g044: Add clock and reset entries for CANFD | Lad Prabhakar | 2021-07-19 | 1 | -0/+4 |
| * | clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] | Geert Uytterhoeven | 2021-07-19 | 4 | -3/+3 |
| * | clk: renesas: r9a07g044: Add GPIO clock and reset entries | Lad Prabhakar | 2021-07-19 | 1 | -0/+5 |
| * | clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries | Biju Das | 2021-07-19 | 1 | -0/+20 |
| * | clk: renesas: r9a07g044: Add USB clocks/resets | Biju Das | 2021-07-19 | 1 | -0/+12 |
| * | clk: renesas: r9a07g044: Add DMAC clocks/resets | Biju Das | 2021-07-19 | 1 | -0/+8 |
| * | clk: renesas: r9a07g044: Add I2C clocks/resets | Biju Das | 2021-07-19 | 1 | -0/+12 |
| * | clk: renesas: r8a779a0: Add the DSI clocks | Kieran Bingham | 2021-07-19 | 1 | -1/+3 |
| * | clk: renesas: r8a779a0: Add the DU clock | Kieran Bingham | 2021-07-19 | 1 | -0/+1 |
| * | clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic | Geert Uytterhoeven | 2021-07-19 | 4 | -4/+4 |
| * | clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() | Lad Prabhakar | 2021-07-19 | 1 | -1/+1 |
| * | clk: renesas: rzg2l: Avoid mixing error pointers and NULL | Dan Carpenter | 2021-07-19 | 1 | -1/+1 |
| * | clk: renesas: rzg2l: Fix a double free on error | Dan Carpenter | 2021-07-19 | 1 | -7/+1 |
| * | clk: renesas: rzg2l: Fix return value and unused assignment | Yang Li | 2021-07-19 | 1 | -4/+2 |
| * | clk: renesas: rzg2l: Remove unneeded semicolon | Yang Li | 2021-07-19 | 1 | -1/+1 |
* | | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds | 2021-08-29 | 1 | -1/+1 |
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| * | clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference | Adam Ford | 2021-08-29 | 1 | -1/+1 |
* | | dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions | Biju Das | 2021-07-12 | 3 | -64/+93 |
* | | clk: renesas: r9a07g044: Add P2 Clock support | Biju Das | 2021-07-12 | 2 | -0/+5 |
* | | clk: renesas: r9a07g044: Fix P1 Clock | Biju Das | 2021-07-12 | 1 | -3/+3 |
* | | clk: renesas: r9a07g044: Rename divider table | Biju Das | 2021-07-12 | 1 | -3/+4 |
* | | clk: renesas: rzg2l: Add multi clock PM support | Biju Das | 2021-07-12 | 1 | -22/+29 |
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* | clk: renesas: Add support for R9A07G044 SoC | Lad Prabhakar | 2021-06-10 | 5 | -0/+141 |
* | clk: renesas: Add CPG core wrapper for RZ/G2L SoC | Lad Prabhakar | 2021-06-10 | 4 | -0/+883 |
* | clk: renesas: r8a77995: Add ZA2 clock | Kuninori Morimoto | 2021-05-27 | 1 | -0/+1 |
* | clk: renesas: cpg-mssr: Make srstclr[] comment block consistent | Geert Uytterhoeven | 2021-05-27 | 1 | -1/+3 |
* | clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions | Geert Uytterhoeven | 2021-05-27 | 1 | -6/+0 |
* | clk: renesas: r9a06g032: Switch to .determine_rate() | Geert Uytterhoeven | 2021-05-11 | 1 | -12/+13 |
* | clk: renesas: div6: Implement range checking | Geert Uytterhoeven | 2021-05-11 | 1 | -1/+7 |
* | clk: renesas: div6: Consider all parents for requested rate | Geert Uytterhoeven | 2021-05-11 | 1 | -3/+32 |
* | clk: renesas: div6: Switch to .determine_rate() | Geert Uytterhoeven | 2021-05-11 | 1 | -5/+7 |
* | clk: renesas: div6: Simplify src mask handling | Geert Uytterhoeven | 2021-05-11 | 1 | -20/+11 |