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path: root/drivers/clk/rockchip/clk-rk3128.c (follow)
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* clk: rockchip: rk3128: Add HCLK_SFCAlex Bee2024-06-231-0/+1
* clk: rockchip: rk3128: Drop CLK_NR_CLKS usageAlex Bee2024-06-081-4/+16
* clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocksAlex Bee2024-05-281-0/+1
* clk: rockchip: rk3128: Export PCLK_MIPIPHYAlex Bee2024-05-281-1/+1
* clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee2023-11-281-1/+1
* clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao2023-11-281-13/+7
* clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li2023-11-161-1/+1
* clk: rockchip: support more core div settingElaine Zhang2021-03-211-3/+4
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: rockchip: add sclk_timer5 as critical clock on rk3128Elaine Zhang2017-09-171-0/+1
* clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs errorElaine Zhang2017-09-171-4/+4
* clk: rockchip: add pclk_pmu as critical clock on rk3128Elaine Zhang2017-09-171-1/+2
* clk: rockchip: modify rk3128 clk driver to also support rk3126Elaine Zhang2017-08-081-14/+55
* clk: rockchip: add clock controller for rk3128Elaine Zhang2017-06-021-0/+612
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-01 03:20:52 +0100