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path: root/drivers/clk/rockchip (follow)
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* clk: rockchip: fix finding of maximum clock IDYao Zi2024-10-101-1/+1
* clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitionsArnd Bergmann2024-09-091-2/+0
* clk: rockchip: fix error for unknown clocksSebastian Reichel2024-08-301-1/+2
* clk: rockchip: rk3588: drop unused codeSebastian Reichel2024-08-301-40/+0
* clk: rockchip: Add clock controller for the RK3576Elaine Zhang2024-08-295-0/+2532
* clk: rockchip: Add new pll type pll_rk3588_ddrElaine Zhang2024-08-292-1/+6
* clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan2024-08-291-1/+1
* clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker2024-08-281-2/+8
* clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: rk3328: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: rk3308: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: rk3288: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: rk3228: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: rk3036: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker2024-08-281-2/+8
* clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman2024-07-291-1/+1
* clk: rockchip: rk3188: Drop CLK_NR_CLKS usageJohan Jonker2024-06-271-4/+14
* clk: rockchip: Switch to use kmemdup_array()Andy Shevchenko2024-06-232-7/+6
* clk: rockchip: rk3128: Add HCLK_SFCAlex Bee2024-06-231-0/+1
* clk: rockchip: rk3128: Drop CLK_NR_CLKS usageAlex Bee2024-06-081-4/+16
* clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocksAlex Bee2024-05-281-0/+1
* clk: rockchip: rk3128: Export PCLK_MIPIPHYAlex Bee2024-05-281-1/+1
* clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach2024-05-041-0/+1
* clk: rockchip: Remove an unused field in struct rockchip_mmc_clockChristophe JAILLET2024-05-041-1/+0
* clk: rockchip: rk3588: Add reset line for HDMI ReceiverShreeya Patel2024-04-101-0/+1
* clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander2024-04-101-0/+4
* clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parentOndrej Jirman2024-02-271-3/+3
* clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel2024-02-271-23/+23
* clk: rockchip: rk3588: fix indentSebastian Reichel2024-02-271-1/+1
* clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel2024-02-271-6/+4
* Merge branch 'v6.9-shared/clkids' into v6.9-clk/nextHeiko Stuebner2024-02-273-1/+23
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| * clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel2024-02-273-1/+23
* | clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan2024-01-251-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2024-01-121-0/+3
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| * clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan2023-11-161-0/+1
* | clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee2023-11-281-1/+1
* | clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao2023-11-281-13/+7
* | clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li2023-11-161-1/+1
* | clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan2023-11-161-0/+1
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* clk: Use device_get_match_data()Rob Herring2023-10-241-7/+2
*-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-302-1/+61
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| | * clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki2023-08-101-0/+59
| | * clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov2023-07-101-1/+1
| | * clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov2023-07-101-0/+1
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* / clk: Explicitly include correct DT includesRob Herring2023-07-192-2/+2
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*-. Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into cl...Stephen Boyd2023-04-252-17/+27
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| | * clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel2023-04-181-16/+26
| | * clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparentQuentin Schulz2023-03-071-1/+1
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