summaryrefslogtreecommitdiffstats
path: root/drivers/clk/samsung (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'v3.18-rockchip-clk2' of ↵Mike Turquette2014-10-012-0/+48
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Allow parent rate changes for i2s on rk3288 and rockchip as well as s3c24xx restart handlers.
| * clk: samsung: register restart handlers for s3c2412 and s3c2443Heiko Stübner2014-10-012-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | S3C2412, S3C2443 and their derivatives contain a special software-reset register in their system-controller. Therefore register a restart handler for those. Tested on a s3c2416-based board, s3c2412 compile-tested. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
* | Merge tag 'for_3.18/samsung-clk' of ↵Mike Turquette2014-09-303-14/+208
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next Samsung clock patches for v3.18 1) non-critical fixes (without the need to push to stable) fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation b511593d7165 clk: samsung: exynos4: fix g3d clocks c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments 22842d244af3 clk: samsung: exynos5260: fix typo in clock name e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1 59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock 5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list 2) Clock driver extensions 07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider 4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
| * clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiationThomas Abraham2014-09-241-4/+3
| | | | | | | | | | | | | | | | | | The 'div_core2' clock and the 'arm_clk' divider clocks are instances of the same divider clock. So remove the 'arm_clk' clock instance. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: fix g3d clocksMarek Szyprowski2014-09-221-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because it does not make any sense and most likely has been added by mistake. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [tomasz.figa@gmail.com: Adjusted commit message.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocksMarek Szyprowski2014-09-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: add missing smmu_g2d clock and update commentsMarek Szyprowski2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | This patch adds missing smmu_g2d clock implementation and updates comment about Exynos4 clocks from 278-282 range. Those clocks are available on all Exynos4 SoC series, so the misleading comment has been removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos3250: Register DMC clk providerKrzysztof Kozlowski2014-09-221-0/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | Add clock provider for clocks in DMC domain including EPLL and BPLL. The DMC clocks are necessary for Exynos3 devfreq driver. The DMC clock domain uses different address space (0x105C0000) than standard clock domain (0x10030000 - 0x10050000). The difference is huge enough to add new DT node for the clock provider, rather than extending existing address space. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos5260: fix typo in clock nameChander Kashyap2014-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The parent name added in parent list as mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different than the defined parent due to typo. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Chander Kashyap <k.chander@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos3250: fix width field of mout_mmc0/1Pankaj Dubey2014-09-221-2/+2
| | | | | | | | | | | | | | | | As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos3250: fix width and shift of div_spi0_isp clockPankaj Dubey2014-09-221-1/+1
| | | | | | | | | | | | | | | | | | Update shift and width field of div_spi0_isp clock as per Exynos3250 user manual. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos3250: fix mout_cam_blk parent listPankaj Dubey2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | As per user manual of Exynos3250 SRC_CAM can select div_cam_blk_320 if it's value is 0xC, so placing div_cam_blk_320 at proper index in parent list of mout_cam_blk. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
* | clk: Remove .owner field for driverKiran Padwal2014-09-261-1/+0
|/ | | | | | | | | | | | | | There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'soc-for-3.17' of ↵Linus Torvalds2014-08-083-0/+1098
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
| * clk: samsung: s5pv210: Remove legacy board supportTomasz Figa2014-07-181-121/+1
| | | | | | | | | | | | | | | | | | Since there is no more support for board files, this patch removes legacy non-DT support from the clock driver as well, including unnecessary clkdev aliases. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: Add S5PV210 Audio Subsystem clock driverTomasz Figa2014-07-182-1/+242
| | | | | | | | | | | | | | | | | | This patch adds a driver for clock controller being a part of Audio Subsystem present on S5PV210 and compatible SoCs. It is used to provide clocks for other IP blocks of this subsystem. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: Add clock driver for S5PV210 and compatible SoCsMateusz Krawczuk2014-07-182-0/+977
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds new, Common Clock Framework-based clock driver for Samsung S5PV210 and compatible SoCs. The driver is just added, without enabling it yet. Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [t.figa: Added support for other SoC variants and clock output. Fixed remaining minor issues.] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | Merge tag 'clk-for-linus-3.17' of ↵Linus Torvalds2014-08-0415-15/+519
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.17 are mostly additions of new clock drivers and fixes/enhancements to existing clock drivers. There are also some non-critical fixes and improvements to the framework core. Changes to the clock framework core include: - improvements to printks on errors - flattening the previously hierarchal structure of per-clock entries in debugfs - allow per-clock debugfs entries that are specific to a particular clock driver - configure initial clock parent and/or initial clock rate from Device Tree - several feature enhancements to the composite clock type - misc fixes New clock drivers added include: - TI Palmas PMIC - Allwinner A23 SoC - Qualcomm APQ8084 and IPQ8064 SoCs - Rockchip rk3188, rk3066 and rk3288 SoCs - STMicroelectronics STiH407 SoC - Cirrus Logic CLPS711X SoC Many fixes, feature enhancements and further clock tree support for existing clock drivers also were merged, such as Samsung's "ARMCLK down" power saving feature for their Exynos4 & Exynos5 SoCs" * tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: Add missing of_clk_set_defaults export clk: checking wrong variable in __set_clk_parents() clk: Propagate any error return from debug_init() clk: clps711x: Add DT bindings documentation clk: Add CLPS711X clk driver clk: st: Use round to closest divider flag clk: st: Update frequency tables for fs660c32 and fs432c65 clk: st: STiH407: Support for clockgenA9 clk: st: STiH407: Support for clockgenD0/D2/D3 clk: st: STiH407: Support for clockgenC0 clk: st: Add quadfs reset handling clk: st: Add polarity bit indication clk: st: STiH407: Support for clockgenA0 clk: st: STiH407: Support for A9 MUX Clocks clk: st: STiH407: Support for Flexgen Clocks clk: st: Adds Flexgen clock binding clk: st: Remove uncessary (void *) cast clk: st: use static const for clkgen_pll_data tables clk: st: use static const for stm_fs tables clk: st: Update ST clock binding documentation ...
| * clk: samsung: register exynos5420 apll/kpll configuration dataThomas Abraham2014-07-261-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Register the PLL configuration data for APLL and KPLL on Exynos5420. This configuration data table specifies PLL coefficients for supported PLL clock speeds when a 24MHz clock is supplied as the input clock source for these PLLs. Cc: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Tested-by: Arjun K.V <arjun.kv@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: Setup clocks before system suspendVikas Sajjan2014-07-261-0/+29
| | | | | | | | | | | | | | | | | | | | | | Prior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked. while at it, add these clks to save/restore list also. Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Make of_device_id array constKrzysztof Kozlowski2014-07-266-6/+6
| | | | | | | | | | | | | | | | | | Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos3250: Enable ARMCLK down featureKrzysztof Kozlowski2014-07-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable ARMCLK down feature on Exynos3250 SoC. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Enable ARMCLK down featureKrzysztof Kozlowski2014-07-261-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Add driver to control CLKOUT line on Exynos SoCsTomasz Figa2014-07-262-0/+154
| | | | | | | | | | | | | | | | This patch introduces a driver that handles configuration of CLKOUT pin of Exynos SoCs that can be used to output certain clocks from inside of the SoC to a dedicated output pin. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Add CLKOUT clock hierarchyTomasz Figa2014-07-261-0/+112
| | | | | | | | | | | | | | | | This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Add missing CPU/DMC clock hierarchyTomasz Figa2014-07-261-0/+50
| | | | | | | | | | | | | | | | This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: exynos4: Add PPMU IP block source clocks.Jonghwa Lee2014-06-301-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Register clk provider only after registering its all clocksSylwester Nawrocki2014-06-3013-9/+34
| | | | | | | | | | | | | | | | | | | | Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2014-07-135-47/+71
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock driver fixes from Mike Turquette: "This batch of fixes is for a handful of clock drivers from Allwinner, Samsung, ST & TI. Most of them are of the "this hardware won't work without this fix" variety, including patches that fix platforms that did not boot under certain configurations. Other fixes are the result of changes to the clock core introduced in 3.15 that had subtle impacts on the clock drivers. There are no fixes to the clock framework core in this pull request" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: spear3xx: Set proper clock parent of uart1/2 clk: spear3xx: Use proper control register offset clk: qcom: HDMI source sel is 3 not 2 clk: sunxi: fix devm_ioremap_resource error detection code clk: s2mps11: Fix double free corruption during driver unbind clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: exynos5420: Remove aclk66_peric from the clock tree description clk/exynos5250: fix bit number for tv sysmmu clock clk: s3c64xx: Hookup SPI clocks correctly clk: samsung: exynos4: Remove SRC_MASK_ISP gates clk: samsung: add more aliases for s3c24xx clk: samsung: fix several typos to fix boot on s3c2410 clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: ti: dra7: return error code in failure case clk: ti: apll: not allocating enough data
| * clk: exynos5420: Remove aclk66_peric from the clock tree descriptionDoug Anderson2014-06-301-30/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "aclk66_peric" clock is a gate clock with a whole bunch of gates underneath it. This big gate isn't very useful to include in our clock tree. If any of the children need to be turned on then the big gate will need to be on anyway. ...and there are plenty of other "big gates" that aren't described in our clock tree, some of which shut off collections of clocks that have no relationship in the hierarchy so are hard to model. "aclk66_peric" is causing earlyprintk problems since it gets disabled as part of the boot process, so let's just remove it. Strangely (and for no good reason) this clock is exported as part of the common clock bindings. Remove it since there are no in-kernel device trees using it and no reason anyone out of tree should refer to it either. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk/exynos5250: fix bit number for tv sysmmu clockRahul Sharma2014-06-301-1/+1
| | | | | | | | | | | | | | | | | | Change bit from 2 to 9 for tv (mixer) sysmmu clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: s3c64xx: Hookup SPI clocks correctlyCharles Keepax2014-06-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the move to this clock driver the hookups for the SPI clocks were dropped, which causes my system Cragganmore (s3c6410 based) to be unable to locate any spibus clocks. This patch adds them back in. When taking the clock from the epll clock (SCLK) the rates on the SPI bus are incorrect, this needs further debugging but the hookup here should be correct and the problem should be else where. The USBCLK case has been dropped because this requires the USB PHY to be enabled. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Remove SRC_MASK_ISP gatesTomasz Figa2014-06-301-12/+4
| | | | | | | | | | | | | | | | | | | | ISP special clocks have dedicated gating registers and so MUX SRC_MASK register should not be used. This patch fixes the problem of Exynos4x12-based boards freezing on system suspend, because those mux outputs need not to be masked while suspending. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: add more aliases for s3c24xxVasily Khoruzhick2014-06-301-0/+5
| | | | | | | | | | | | | | | | | | Without these aliases clock lookup fails in s3c2410fb, s3cmci, s3c2410-nand, s3c24xx-i2s, and i2c-s3c2410 drivers. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: fix several typos to fix boot on s3c2410Vasily Khoruzhick2014-06-301-2/+2
| | | | | | | | | | | | | | | | | | | | There's a several typos in a driver: 2410 instead of S3C2410 and wrong argument to ARRAY_SIZE(). They prevent s3c2410 from properly booting. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | clk: exynos5420: Add IDs for clocks used in PD mfcArun Kumar K2014-07-111-2/+4
|/ | | | | | | | | | Adds IDs for MUX clocks to be used by power domain for MFC for doing re-parenting while pd on/off. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Merge tag 'clk-for-linus-3.16' of ↵Linus Torvalds2014-06-081-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux into next Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.16 are pretty typical: mostly clock driver additions and fixes. There are additions to the clock core code for some of the basic types (e.g. the common divider type has some fixes and featured added to it). One minor annoyance is a last-minute dependency that wasn't handled quite right. Commit ba0fae3b06a6 ("clk: berlin: add core clock driver for BG2/BG2CD") in this pull request depends on include/dt-bindings/clock/berlin2.h, which is already in your tree via the arm-soc pull request. Building for the berlin platform will break when the clk tree is built on it's own, but merged into your master branch everything should be fine" * tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits) mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs clk: export __clk_round_rate for providers clk: versatile: free icst on error return clk: qcom: Return error pointers for unimplemented clocks clk: qcom: Support msm8974pro global clock control hardware clk: qcom: Properly support display clocks on msm8974 clk: qcom: Support display RCG clocks clk: qcom: Return highest rate when round_rate() exceeds plan clk: qcom: Fix mmcc-8974's PLL configurations clk: qcom: Fix clk_rcg2_is_enabled() check clk: berlin: add core clock driver for BG2Q clk: berlin: add core clock driver for BG2/BG2CD clk: berlin: add driver for BG2x complex divider cells clk: berlin: add driver for BG2x simple PLLs clk: berlin: add driver for BG2x audio/video PLL clk: st: Terminate of match table clk/exynos4: Fix compilation warning ARM: shmobile: r8a7779: Add clock index macros for DT sources clk: divider: Fix overflow in clk_divider_bestdiv clk: u300: Terminate of match table ...
| * clk/exynos4: Fix compilation warningSachin Kamat2014-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following warning: WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown) The function exynos4_clk_sleep_init() references the (unknown reference) __initdata (unknown). This is often because exynos4_clk_sleep_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'drivers-for-3.16' of ↵Linus Torvalds2014-06-031-0/+42
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull ARM SoC driver changes from Olof Johansson: "SoC-near driver changes that we're merging through our tree. Mostly because they depend on other changes we have staged, but in some cases because the driver maintainers preferred that we did it this way. This contains a largeish cleanup series of the omap_l3_noc bus driver, cpuidle rework for Exynos, some reset driver conversions and a long branch of TI EDMA fixes and cleanups, with more to come next release. The TI EDMA cleanups is a shared branch with the dmaengine tree, with a handful of Davinci-specific fixes on top. After discussion at last year's KS (and some more on the mailing lists), we are here adding a drivers/soc directory. The purpose of this is to keep per-vendor shared code that's needed by different drivers but that doesn't fit into the MFD (nor drivers/platform) model. We expect to keep merging contents for this hierarchy through arm-soc so we can keep an eye on what the vendors keep adding here and not making it a free-for-all to shove in crazy stuff" * tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM tty: serial: msm: Remove direct access to GSBI power: reset: keystone-reset: introduce keystone reset driver Documentation: dt: add bindings for keystone pll control controller Documentation: dt: add bindings for keystone reset driver soc: qcom: fix of_device_id table ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos ARM: EXYNOS: Move the driver to drivers/cpuidle directory ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c ARM: EXYNOS: Pass the AFTR callback to the platform_data ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier ARM: EXYNOS: Move the AFTR state function into pm.c ARM: EXYNOS: Encapsulate the AFTR code into a function ARM: EXYNOS: Disable cpuidle for exynos5440 ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle ARM: EXYNOS: Remove ifdef for scu_enable in pm ARM: EXYNOS: Move scu_enable in the cpu_pm notifier ARM: EXYNOS: Use the cpu_pm notifier for pm ...
| * \ Merge tag 'samsung-drivers-2' of ↵Olof Johansson2014-05-311-0/+35
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim: This is including fix exynos cpufreq driver compilation with ARCH_MULTIPLATFORM. Even though this is a work around, this is required for support exynos multiplatform for a while and will be updated in near future. This is based on tags/samsung-exynos. * tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits) cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks cpufreq: exynos: Fix the compile error ARM: S3C24XX: move debug-macro.S into the common space ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro ARM: S3C24XX: trim down debug uart handling ARM: compressed/head.S: remove s3c24xx special case ARM: EXYNOS: Remove unnecessary inclusion of cpu.h ARM: EXYNOS: Migrate Exynos specific macros from plat to mach ARM: EXYNOS: Remove exynos_subsys registration ARM: EXYNOS: Remove duplicate lines in Makefile ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling ARM: dts: Remove g2d_pd node for exynos5420 ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: EXYNOS: Move arm core power down clock to exynos5250 common clockAmit Daniel Kachhap2014-05-251-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform. Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsugn.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> [t.figa: Rebased onto current kernel sources.] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | Merge tag 'soc-for-3.16' of ↵Linus Torvalds2014-06-0318-548/+4771
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull part one of ARM SoC updates from Olof Johansson: "A quite large set of SoC updates this cycle. In no particular order: - Multi-cluster power management for Samsung Exynos, adding support for big.LITTLE CPU switching on EXYNOS5 - SMP support for Marvell Armada 375 and 38x - SMP rework on Allwinner A31 - Xilinx Zynq support for SOC_BUS, big endian - Marvell orion5x platform cleanup, modernizing the implementation and moving to DT. - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so that their platform can be enabled in the same kernel binary as most of the other v7 platforms in the tree. \o/ The work isn't quite complete, there's some driver fixes still needed, but the basics now work. New SoC support added: - Freescale i.MX6SX - LSI Axxia AXM55xx SoCs - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800 - STi STIH407 plus a large set of various smaller updates for different platforms. I'm probably missing some important one here" * tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits) ARM: exynos: don't run exynos4 l2x0 setup on other platforms ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug ARM: EXYNOS: mcpm rename the power_down_finish ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5410: register clocks using common clock framework ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 ARM: sunxi: allow building without reset controller Documentation: devicetree: arm: sort enable-method entries ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks ARM: dts: axxia: Add reset controller power: reset: Add Axxia system reset driver ARM: axxia: Adding defconfig for AXM55xx ...
| * | | | clk: exynos5410: register clocks using common clock frameworkTarek Dakhran2014-05-302-0/+210
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocksCho KyongHo2014-05-251-0/+35
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | clk: exynos5420: Add 5800 specific clocksAlim Akhtar2014-05-191-56/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos5800 clock structure is mostly similar to 5420 with only a small delta changes. So the 5420 clock file is re-used for 5800 also. The common clocks for both are seggreagated and few clocks which are different for both are separately initialized. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | clk: samsung: exynos3250: Add clocks using common clock frameworkTomasz Figa2014-05-142-0/+781
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Karol Wrona <k.wrona@samsung.com> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
| * | ARM: S3C24XX: move S3C24XX clock Kconfig options to Samsung clock Kconfig filePankaj Dubey2014-05-141-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves S3C24XX specific clock Kconfig options into "clk/samsung/Kconfig" and also removes COMMON_CLK selection from "mach-s3c24xx/Kconfig" as S3C24XX_COMMON_CLK is selecting it's dependency. CC: Ben Dooks <ben-linux@fluff.org> CC: Kukjin Kim <kgene.kim@samsung.com> CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * | clk: samsung: add new Kconfig for Samsung common clock optionPankaj Dubey2014-05-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new Kconfig file for adding new COMMON_CLK_SAMSUNG option. Samsung platforms can select this for using common clock infrastructure. CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * | clk: samsung: exynos5420: add more registers to restore listShaik Ameer Basha2014-05-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds more register offsets to the list for preserving their values during S2R. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * | clk: samsung: exynos5420: add misc clocksShaik Ameer Basha2014-05-141-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some missing miscellaneous clocks specific to exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 02:07:25 +0100