summaryrefslogtreecommitdiffstats
path: root/drivers/clk/samsung (follow)
Commit message (Collapse)AuthorAgeFilesLines
* clk: samsung: exynos850: Make PMU_ALIVE_PCLK criticalSam Protsenko2023-03-131-1/+1
| | | | | | | | | | PMU_ALIVE_PCLK is needed for PMU registers access, and it must be always running, as not only the kernel accesses PMU registers. Make it critical to ensure that. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230308233822.31180-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Convert to platform remove callback returning voidUwe Kleine-König2023-03-122-8/+4
| | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230312161512.2715500-25-u.kleine-koenig@pengutronix.de Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: exynos5433: Extract PM support to common ARM64 layerSam Protsenko2023-03-073-156/+180
| | | | | | | | | | | Exynos5433 clock driver implements PM support internally, which might be also useful for other Exynos clock drivers. Extract all PM related code from clk-exynos5433 to common ARM64 functions. Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230307002423.24454-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Extract parent clock enabling to common functionSam Protsenko2023-03-071-16/+41
| | | | | | | | | | Extract parent clock enabling from exynos_arm64_register_cmu() to dedicated function. Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230307002423.24454-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Extract clocks registration to common functionSam Protsenko2023-03-072-18/+30
| | | | | | | | | | | | | It might be useful to have a separate clocks registration function, so it can be called from different users. Extract that common code from samsung_cmu_register_one() to samsung_cmu_register_clocks(). Also make that new function global as it's going to be used in other modules further. Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230307002423.24454-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: exynos850: Add AUD and HSI main gate clocksSam Protsenko2023-03-061-0/+19
| | | | | | | | | | | | | | | | | Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20230223042133.26551-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: exynos850: Implement CMU_G3D domainSam Protsenko2023-03-061-0/+120
| | | | | | | | | | | | | | | | | | | CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for BLK_G3D. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_G3D - all internal CMU_G3D clocks - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and SysReg G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223042133.26551-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: clk-pll: Implement pll0818x PLL typeSam Protsenko2023-03-062-0/+2
| | | | | | | | | | | | | | pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, pll0818x is the same as pll0822x. The only difference is: - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) Add pll0818x type as an alias to pll0822x. Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223042133.26551-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Set dev in samsung_clk_init()Sam Protsenko2023-03-068-13/+24
| | | | | | | | | | | | | Some drivers set dev to context in order to implement PM. Make that part of samsung_clk_init() instead of assigning `ctx->dev = dev' separately. No functional change. Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Don't pass reg_base to samsung_clk_register_pll()Sam Protsenko2023-03-069-20/+16
| | | | | | | | | | | | | | Base address can be derived from context structure. Remove `base' argument from samsung_clk_register_pll() and use `ctx->reg_base' instead, as it's done in other clock registering functions. No functional change. Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: Remove np argument from samsung_clk_init()Sam Protsenko2023-03-068-11/+10
| | | | | | | | | | | | | | The code using `np' argument was removed from samsung_clk_init(). Remove that leftover parameter as well. No functional change. Fixes: d5e136a21b20 ("clk: samsung: Register clk provider only after registering its all clocks") Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: remove s3c24xx specific pll bitsArnd Bergmann2023-01-162-202/+0
| | | | | | | | | | With the s3c24xx clk driver gone, the portions of the pll driver for it can also be removed. Suggested-by: Chanwoo Choi <cwchoi00@gmail.com> Link: https://lore.kernel.org/linux-arm-kernel/0e0eff12-d8ea-72e9-d135-4259dda9a750@gmail.com/ Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* clk: remove s3c24xx driverArnd Bergmann2023-01-166-1614/+0
| | | | | | | | | The s3c24xx platform is gone, so the clk driver can be removed as well. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
*-. Merge branches 'clk-x86', 'clk-xilinx', 'clk-cleanup', 'clk-mstar' and ↵Stephen Boyd2022-12-122-2/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-ingenic' into clk-next - Make MxL's CGU driver secure compatible - Support for CPU PLL on MStar/SigmaStar SoCs - Ingenic JZ4755 SoC clk support - Support audio clks on X1000 SoCs * clk-x86: clk: mxl: syscon_node_to_regmap() returns error pointers clk: mxl: Fix a clk entry by adding relevant flags clk: mxl: Add option to override gate clks clk: mxl: Remove redundant spinlocks clk: mxl: Switch from direct readl/writel based IO to regmap based IO * clk-xilinx: clk: xilinx: Drop duplicate depends on COMMON_CLK * clk-cleanup: clk: nomadik: correct struct name kernel-doc warning clk: lmk04832: fix kernel-doc warnings clk: lmk04832: drop superfluous #include clk: lmk04832: drop unnecessary semicolons clk: lmk04832: declare variables as const when possible clk: socfpga: Fix memory leak in socfpga_gate_init() clk: st: Fix memory leak in st_of_quadfs_setup() clk: samsung: Fix memory leak in _samsung_clk_register_pll() clk: visconti: Fix memory leak in visconti_register_pll() clk: Remove a useless include clk: samsung: Fix reference to CLK_OF_DECLARE in comment clk: stm32mp1: Staticize ethrx_src clk: keystone: syscon-clk: Use dev_err_probe() helper clk: bulk: Use dev_err_probe() helper in __clk_bulk_get() clk: cdce925: simplify using devm_regulator_get_enable() * clk-mstar: clk: mstar: msc313 cpupll clk driver * clk-ingenic: clk: Add Ingenic JZ4755 CGU driver dt-bindings: clock: Add Ingenic JZ4755 CGU header dt-bindings: ingenic: Add support for the JZ4755 CGU clk: ingenic: Minor cosmetic fixups for X1000 clk: ingenic: Add X1000 audio clocks dt-bindings: ingenic,x1000-cgu: Add audio clocks clk: ingenic: Add .set_rate_hook() for PLL clocks clk: ingenic: Make PLL clock enable_bit and stable_bit optional clk: ingenic: Make PLL clock "od" field optional
| | * clk: samsung: Fix memory leak in _samsung_clk_register_pll()Xiu Jianfeng2022-12-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If clk_register() fails, @pll->rate_table may have allocated memory by kmemdup(), so it needs to be freed, otherwise will cause memory leak issue, this patch fixes it. Fixes: 3ff6e0d8d64d ("clk: samsung: Add support to register rate_table for samsung plls") Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com> Link: https://lore.kernel.org/r/20221123032015.63980-1-xiujianfeng@huawei.com Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: samsung: Fix reference to CLK_OF_DECLARE in commentJonathan Neuschäfer2022-11-011-2/+2
| |/ | | | | | | | | | | | | | | It was misspelled as OF_CLK_DECLARE. Fix it. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221031220751.158341-1-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: samsung: Revert "clk: samsung: exynos-clkout: Use ↵Marek Szyprowski2022-11-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_get_match_data()" of_device_get_match_data() function should not be used on the device other than the one matched to the given driver, because it always returns the match_data of the matched driver. In case of exynos-clkout driver, the code matched the OF IDs on the PARENT device, so replacing it with of_device_get_match_data() broke the driver. This reverts commit 777aaf3d1daf793461269b49c063aca1cee06a44. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Fixes: 777aaf3d1daf ("clk: samsung: exynos-clkout: Use of_device_get_match_data()") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221108213718.32076-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* | clk: samsung: exynos7885: Correct "div4" clock parentsDavid Virag2022-10-181-2/+2
|/ | | | | | | | | | | | | | "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by 2 to achieve a by 4 division, thus their parents are the respective "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents. This leads to the kernel thinking "div4"s and everything under them run at 2x the clock speed. Fix this. Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver") Signed-off-by: David Virag <virag.david003@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20221013151341.151208-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* clk: samsung: exynos850: Implement CMU_MFCMSCL domainSam Protsenko2022-08-231-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec), JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_MFCMSCL - all internal CMU_MFCMSCL clocks - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller), JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler), MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-8-semen.protsenko@linaro.org
* clk: samsung: exynos850: Implement CMU_IS domainSam Protsenko2022-08-231-0/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CMU_IS clock domain provides clocks for IS IP-core (Image Signal Processing Subsystem). According to Exynos850 TRM, CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_IS - all internal CMU_IS clocks - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave), D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric Distortion Correction), IPP (Image Preprocessing Processing core), ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler), VRA (Visual Recognition Accelerator), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-7-semen.protsenko@linaro.org
* clk: samsung: exynos850: Implement CMU_AUD domainSam Protsenko2022-08-231-0/+302
| | | | | | | | | | | | | | | | | | | | | | | | | CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem). According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_AUD - all internal CMU_AUD clocks - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge), DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone Protection Controller), GPIO, PPMU (Platform Performance Monitoring Unit), SysMMU, SysReg and WDT ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Once ABOX driver is implemented, maybe it can be handled there instead. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-6-semen.protsenko@linaro.org
* clk: samsung: exynos850: Style fixesSam Protsenko2022-08-231-3/+2
| | | | | | | | | | Fix some typos in comments and do small coding style improvements. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-5-semen.protsenko@linaro.org
* clk: samsung: exynosautov9: add fsys1 clock supportChanho Park2022-08-231-0/+130
| | | | | | | | | | | | CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
* clk: samsung: exynosautov9: add fsys0 clock supportChanho Park2022-08-231-0/+243
| | | | | | | | | | | CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 Lanes. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/ae84d4a0487a5299076bfeef5732579f5207acf9.1659054220.git.chanho61.park@samsung.com
* clk: samsung: exynosautov9: correct register offsets of peric0/c1Chanho Park2022-08-231-10/+10
| | | | | | | | | | | | | Some register offsets of peric0 and peric1 cmu blocks need to be corrected and re-ordered by numerical order. Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support") Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727021357.152421-4-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add missing gate clks for peric0/c1Chanho Park2022-08-231-0/+8
| | | | | | | | | | | "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 and peric1 respectively. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727021357.152421-3-chanho61.park@samsung.com
* clk: samsung: exynos7885: Add TREX clocksDavid Virag2022-08-231-7/+42
| | | | | | | | | | | | | | | | | | | TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. When clocks are cut from TREX D Core, the eMMC and the framebuffer stops working properly. Other unknown things may stop working as well. When clocks are cut from TREX P Core, the system locks up needing a hard reset. Add these clocks and mark them critical so that they are always on. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-5-virag.david003@gmail.com
* clk: samsung: exynos7885: Implement CMU_FSYS domainDavid Virag2022-08-231-0/+158
| | | | | | | | | | | | | | CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks for all MMC devices on Exynos7885, and USB30DRD. Add clocks: - Bus clocks in CMU_TOP needed for CMU_FSYS - All clocks in CMU_FSYS needed for MMC devices Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-4-virag.david003@gmail.com
* clk: samsung: exynos-clkout: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)2022-08-231-4/+2
| | | | | | | | Use of_device_get_match_data() to simplify the code. Signed-off-by: Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220307033546.2075097-1-chi.minghao@zte.com.cn
* clk: samsung: exynosautov9: add cmu_peric1 clock supportChanho Park2022-05-101-0/+254
| | | | | | | | | | Like CMU_PERIC0, this provides clocks for USI06 ~ USI11 and USI_I2C. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-10-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add cmu_peric0 clock supportChanho Park2022-05-101-0/+254
| | | | | | | | | | CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5 have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add cmu_fsys2 clock supportChanho Park2022-05-101-0/+69
| | | | | | | | | | | | CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes ufs and ethernet IPs. This patch adds some essential clocks to be controlled by ethernet/ufs drivers instead of listing full clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-8-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add cmu_busmc clock supportChanho Park2022-05-101-0/+55
| | | | | | | | | | | | CMU_BUSMC is responsible to control clocks of BLK_BUSMC which represents Data/Peri buses. Most clocks except PDMA/SPDMA are not necessary to be controlled by HLOS. So, this adds PDMA/SPDMA gate clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-7-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add cmu_peris clock supportChanho Park2022-05-101-0/+51
| | | | | | | | | | | | CMU_PERIS is responsible to control clocks of BLK_PERIS which has OPT/MCT/WDT and TMU. This patch only supports WDT gate clocks and all other clocks except WDT will be supported later. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-6-chanho61.park@samsung.com
* clk: samsung: exynosautov9: add cmu_core clock supportChanho Park2022-05-101-0/+92
| | | | | | | | | | | | | | Add CMU_CORE clock which represents Core BUS clocks. The source clocks of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source clocks should be provided via device tree. All the gate clocks are defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus clocks but not been assigned to any drivers. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com
* clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park2022-05-102-0/+959
| | | | | | | | | | | | | This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block and they will generate bus clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
* clk: samsung: fix missing Tesla FSD dependency on ExynosKrzysztof Kozlowski2022-02-011-0/+1
| | | | | | | | | | | | | | | The Tesla FSD clock controller driver uses shared parts from Exynos ARM64 clock drivers, so add proper dependency to fix COMPILE_TEST build errors like: /usr/bin/aarch64-linux-gnu-ld: drivers/clk/samsung/clk-fsd.o: in function `fsd_cmu_probe': clk-fsd.c:(.init.text+0x9c): undefined reference to `exynos_arm64_register_cmu' Reported-by: kernel test robot <lkp@intel.com> Fixes: e3f3dc3810d3 ("clk: samsung: fsd: Add cmu_peric block clock information") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220129173407.278591-1-krzysztof.kozlowski@canonical.com
* clk: samsung: fsd: Add cam_csi block clock informationAlim Akhtar2022-01-261-0/+207
| | | | | | | | | | | | | Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work. Cc: linux-fsd@tesla.com Signed-off-by: Sathyakam M <sathya@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-11-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add cmu_mfc block clock informationAlim Akhtar2022-01-261-0/+121
| | | | | | | | | | | | | | Adds cmu_mfc clock related code, these clocks are required for MFC IP. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy <smitha.t@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-10-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add cmu_imem block clock informationAlim Akhtar2022-01-261-0/+283
| | | | | | | | | | | | | | | | Adds cmu_imem clock related code, imem block contains IPs like WDT, DMA, TMU etc, these clocks are required for such IP function. Cc: linux-fsd@tesla.com Signed-off-by: Arjun K V <arjun.kv@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tauseef Nomani <tauseef.n@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-9-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add cmu_fsys1 clock informationAlim Akhtar2022-01-261-0/+175
| | | | | | | | | | | | | | Adds cmu_fsys1 block clock information which are needed for PCIe IPs in block FSYS1. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-8-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add cmu_fsys0 clock informationAlim Akhtar2022-01-261-0/+302
| | | | | | | | | | | | | | | | CMU_FSYS0 block has IPs like UFS, EQOS, PCIe etc, lets add the related clock information for the same. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-7-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add cmu_peric block clock informationAlim Akhtar2022-01-261-0/+405
| | | | | | | | | | | | | | | | | | | Add CMU_PERIC block clock information needed for various IPs functions found in this block. Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com> Signed-off-by: Chandrasekar R <rcsekar@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Sriranjani P <sriranjani.p@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-6-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: fsd: Add initial clock supportAlim Akhtar2022-01-265-0/+321
| | | | | | | | | | | | | | Add initial clock support for FSD (Full Self-Driving) SoC which is required to bring-up platforms based on this SoC. Cc: linux-fsd@tesla.com Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-5-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* clk: samsung: Add initial Exynos7885 clock driverDavid Virag2021-12-192-0/+598
| | | | | | | | | | | | | | | | | | | This is an initial implementation adding basic clocks, such as UART, USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which was made by Sam Protsenko, thus the copyright and author lines were kept. Bus clocks are enabled by default as well to avoid hangs while trying to access CMU registers. Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of CMU_CORE, and most of CMU_PERI is implemented as of now. Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211206153124.427102-7-virag.david003@gmail.com
* clk: samsung: clk-pll: Add support for pll1417xDavid Virag2021-12-192-0/+2
| | | | | | | | | | | | | | | | | | pll1417x is used in Exynos7885 SoC for top-level integer PLLs. It is similar enough to pll0822x that practically the same code can handle both. The difference that's to be noted is that when defining a pl1417x PLL, the "con" parameter of the PLL macro should be set to the CON1 register instead of CON3, like this: PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL), Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com
* clk: samsung: Make exynos850_register_cmu sharedDavid Virag2021-12-194-84/+119
| | | | | | | | | | | | | | | Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it to a new file called "clk-exynos-arm64.c". This should have no functional changes, but it will allow this code to be shared between other arm64 Exynos SoCs, like the Exynos7885 and possibly ExynosAuto V9. Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211206153124.427102-5-virag.david003@gmail.com
* clk: samsung: exynos850: Add missing sysreg clocksSam Protsenko2021-12-191-0/+29
| | | | | | | | | | | | | | | System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211217161549.24836-3-semen.protsenko@linaro.org
* clk: samsung: exynos850: Register clocks earlySam Protsenko2021-11-221-21/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks must be registered before init calls. For example MCT clock (from CMU_PERI) is needed for MCT timer driver, which is registered with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for clk-exynos850 platform driver init, it's already too late. Inability to get "mct" clock in MCT driver leads to kernel panic, as functions registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver can't be fixed either, as it's acting as a clock source and it's essential to register it in start_kernel() -> time_init(). Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP generates clocks needed for CMU_PERI, but it's already registered early. While at it, let's cleanup the code a bit, by extracting everything related to CMU initialization and registration to the separate function. Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support"), as well as in drivers/clk/mediatek/clk-mt2712.c. [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org
* clk: samsung: exynos850: Keep some crucial clocks runningSam Protsenko2021-11-221-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks shouldn't be automatically disabled in clk_disable_unused(), otherwise kernel hangs. Mark those clocks with: - CLK_IS_CRITICAL flag, when there won't be any consumers for that clock, but system can't function when it's gated - CLK_IGNORE_UNUSED flag, when consumer driver will be probably added later That makes it possible to run the kernel without passing the "clk_ignore_unused" param. Next clocks were modified: - "gout_dpu_cmu_dpu_pclk": CLK_IGNORE_UNUSED Will be enabled later in DSIM driver (Display Serial Interface Master). - "gout_gpio_peri_pclk": CLK_IGNORE_UNUSED "gout_gpio_cmgp_pclk": CLK_IGNORE_UNUSED "gout_gpio_hsi_pclk": CLK_IGNORE_UNUSED Should be probably enabled in corresponding GPIO driver later, or made CLK_IS_CRITICAL. "gout_gpio_peri_clk" is actually used by LEDs on Exynos850-based dev board, so kernel hangs if this clock is not running. Other clocks were marked as "ignore unused" to prevent similar issues for other use cases or boards that might be added later. - "gout_cci_aclk": CLK_IS_CRITICAL CCI (Cache Coherent Interconnect): obviously is critical. - "gout_gic_clk": CLK_IS_CRITICAL GIC (Generic Interrupt Controller): obviously is critical. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211121232741.6967-7-semen.protsenko@linaro.org
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 11:40:12 +0100