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* clk: exynos-audss: add support for Exynos 5420Andrew Bresticker2014-01-081-7/+33
| | | | | | | | | | The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker2014-01-081-1/+1
| | | | | | | | | | | | There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos-audss: allow input clocks to be specified in device treeAndrew Bresticker2014-01-081-5/+20
| | | | | | | | | | | This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos-audss: convert to platform deviceAndrew Bresticker2014-01-081-16/+88
| | | | | | | | | | | | | | | | | | The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5440: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-47/+34
| | | | | | | | | | | The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5420: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-339/+309
| | | | | | | | | | | The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-295/+264
| | | | | | | | | | | The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos4: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-455/+402
| | | | | | | | | | | The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: register APLL rate tableAndrew Bresticker2014-01-081-1/+24
| | | | | | | | | Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat2013-12-301-1/+2
| | | | | | | | | Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa2013-12-301-3/+5
| | | | | | | | | This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa2013-12-301-3/+3
| | | | | | | | | | According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa2013-12-301-4/+12
| | | | | | | | | | | This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa2013-12-301-6/+8
| | | | | | | | | This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa2013-12-301-8/+17
| | | | | | | | | | This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa2013-12-301-122/+123
| | | | | | | | | | This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa2013-12-301-102/+188
| | | | | | | | | | | | | This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* Merge branch 'samsung-fixes' into samsung-next-baseTomasz Figa2013-12-303-11/+15
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| * clk: exynos: File scope reg_save array should depend on PM_SLEEPKrzysztof Kozlowski2013-12-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only by suspend and resume functions. This fixes the warning on CONFIG_PM_SLEEP=n: drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan2013-12-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan2013-12-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan2013-12-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker2013-12-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos4: Correct SRC_MFC registerSeung-Woo Kim2013-12-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | clk: exynos5420: fix cpll clock register offsetsChander Kashyap2013-12-041-2/+2
|/ | | | | | | | Fixes cpll control and lock register offset values for Exynos5420 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* ARM: S3C64XX: Migrate clock handling to Common Clock FrameworkTomasz Figa2013-09-161-2/+0
| | | | | | | | This patch migrates the s3c64xx platform to use the new clock driver using Common Clock Framework. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-1011-508/+1702
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
| * clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa2013-09-061-10/+2
| | | | | | | | | | | | | | | | | | | | | | Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4x12Tomasz Figa2013-09-061-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4210Tomasz Figa2013-09-061-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Reorder registration of mout_vpllsrcTomasz Figa2013-09-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL46xxTomasz Figa2013-09-062-1/+135
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL46xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL46xxTomasz Figa2013-09-063-65/+14
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL45xxTomasz Figa2013-09-062-1/+119
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL45xxTomasz Figa2013-09-063-62/+20
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_pllsTomasz Figa2013-09-061-3/+3
| | | | | | | | | | | | | | | | | | | | This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove checks for DT nodeTomasz Figa2013-09-061-7/+4
| | | | | | | | | | | | | | | | | | | | Exynos 4 supports only DT based bootup, so non-DT cases does not need to be handled anymore. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove unused static clkdev aliasesTomasz Figa2013-09-061-184/+172
| | | | | | | | | | | | | | | | | | | | | | Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: Modify _get_rate() helper to use __clk_lookup()Tomasz Figa2013-09-063-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to use clkdev inside the clock driver to retrieve the clocks for internal use. Instead __clk_lookup() helper can be used to look up clocks by their platform name. This patch modifies the behavior of _get_rate() helper to look up clocks by platform name and adjusts all users of it to pass platform names instead of clkdev aliases. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Use separate aliases for cpufreq related clocksTomasz Figa2013-09-061-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: assign dout_pixel id to pixel clock dividerRahul Sharma2013-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add hdmi mux to change parents in hdmi driverRahul Sharma2013-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: fix the order of parents of hdmi muxRahul Sharma2013-08-301-1/+1
| | | | | | | | | | | | | | | | | | Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add gate clock for mixer sysmmuRahul Sharma2013-08-301-1/+2
| | | | | | | | | | | | | | | | Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add sclk_hdmiphy to the list of special clocksRahul Sharma2013-08-301-2/+2
| | | | | | | | | | | | | | | | | | Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma2013-08-291-2/+2
| | | | | | | | | | | | | | | | | | parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: s3c64xx: Fix incorrect placement of __initdataSachin Kamat2013-08-281-2/+2
| | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge branch 'clk-next-s3c64xx-delta' into clk-nextMike Turquette2013-08-282-98/+13
| |\
| | * clk: samsung: pll: Use new registration method for PLL6552 and PLL6553Tomasz Figa2013-08-272-98/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-192-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-05 09:02:06 +0100