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* ARM: shmobile: r8a7778: common clock framework CPG driverUlrich Hecht2015-02-272-0/+144
| | | | | | | | | Driver for the r8a7778's clocks that depend on the mode bits. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-214-4/+345
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * clk: shmobile: div6: Avoid division by zero in .round_rate()Geert Uytterhoeven2015-02-041-0/+3
| | | | | | | | | | | | | | | | | | Anyone may call clk_round_rate() with a zero rate value, so we have to protect against that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: shmobile: Add R-Car Gen2 ADSP clock supportSergei Shtylyov2015-01-081-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Add R-Car Gen2 RCAN clock supportSergei Shtylyov2015-01-081-0/+40
| | | | | | | | | | | | | | | | | | | | Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the RCANCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but has no divider field, and so can't be supported by that driver... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: r8a73a4 common clock framework implementationUlrich Hecht2015-01-082-0/+242
| | | | | | | | | | | | | | | | | | | | Driver for the R8A73A4's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Michael Turquette <mturquette@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Add r8a7793 supportHisashi Nakamura2015-01-081-0/+1
| | | | | | | | | | | | | | | | R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: div6: Avoid changing divisor in .disable()Geert Uytterhoeven2015-01-081-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While DIV6 clocks require the divisor field to be non-zero when stopping the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later if the divisor field is changed when stopping the clock. The reason for this is unknown. To fix this, do not touch the divisor field if it's already non-zero. On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0 Bus State Controller, which is clocked by the ZB clock. Without this fix, if the ZB clock is disabled during system suspend, and re-enabled during resume, the kernel locks up when the smsc911x driver tries to access the Ethernet registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* | clk: shmobile: fix sparse NULL pointer warningWei Yongjun2015-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes the following sparse warnings: drivers/clk/shmobile/clk-sh73a0.c:57:17: warning: Using plain integer as NULL pointer Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: shmobile: sh73a0 common clock framework implementationUlrich Hecht2014-12-212-0/+219
|/ | | | | | | | | | | Driver for the SH73A0's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* clk: shmobile: div6: support selectable-input clocksUlrich Hecht2014-11-121-12/+101
| | | | | | | | | Support for setting the parent at initialization time based on the current hardware configuration in DIV6 clocks with selectable parents as found in the r8a73a4, r8a7740, sh73a0, and other SoCs. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge tag 'clk-for-linus-3.18' of ↵Linus Torvalds2014-10-151-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock tree updates from Mike Turquette: "The clk tree changes for 3.18 are dominated by clock drivers. Mostly fixes and enhancements to existing drivers as well as new drivers. This tag contains a bit more arch code than I usually take due to some OMAP2+ changes. Additionally it contains the restart notifier handlers which are merged as a dependency into several trees. The PXA changes are the only messy part. Due to having a stable tree I had to revert one patch and follow up with one more fix near the tip of this tag. Some dead code is introduced but it will soon become live code after 3.18-rc1 is released as the rest of the PXA family is converted over to the common clock framework. Another trend in this tag is that multiple vendors have started to push the complexity of changing their CPU frequency into the clock driver, whereas this used to be done in CPUfreq drivers. Changes to the clk core include a generic gpio-clock type and a clk_set_phase() function added to the top-level clk.h api. Due to some confusion on the fbdev mailing list the kernel boot parameters documentation was updated to further explain the clk_ignore_unused parameter, which is often required by users of the simplefb driver. Finally some fixes to the locking around the clock debugfs stuff was done to prevent deadlocks when interacting with other subsystems." * tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux: (99 commits) clk: pxa clocks build system fix Revert "arm: pxa: Transition pxa27x to clk framework" clk: samsung: register restart handlers for s3c2412 and s3c2443 clk: rockchip: add restart handler clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate doc/kernel-parameters.txt: clarify clk_ignore_unused arm: pxa: Transition pxa27x to clk framework dts: add devicetree bindings for pxa27x clocks clk: add pxa27x clock drivers arm: pxa: add clock pll selection bits clk: dts: document pxa clock binding clk: add pxa clocks infrastructure clk: gpio-gate: Ensure gpiod_ APIs are prototyped clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe clk: ti: LLVMLinux: Move __init outside of type definition clk: ti: consider the fact that of_clk_get() might return an error clk: ti: dra7-atl-clock: fix a memory leak clk: ti: change clock init to use generic of_clk_init clk: hix5hd2: add I2C clocks clk: hix5hd2: add watchdog0 clocks ...
| * clk: shmobile: add missing 0x0100 for SDCKCRKuninori Morimoto2014-09-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 10cdfe9f327ab8d120cf6957e58c6203e3a53847 (clk: shmobile: Add R-Car Gen2 clocks support) added R-Car Gen2 clock support via DT for v3.14. But, cpg_sd01_div_table is missing "0x0100: x 1/8" division ratio. This patch fixes hidden bug. It is based on R-Car H2 v0.7, R-Car M2 v0.9. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge branch 'kbuild' of ↵Linus Torvalds2014-10-141-2/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild Pull kbuild changes from Michal Marek: - fix for handling dependencies of *-objs targets by Masahiro Yamada - lots of cleanups in the kbuild machinery, also by Masahiro - fixes for the kconfig build to use an UTF-8 capable ncurses library if possible and to build on not-so-standard installs - some more minor fixes * 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild: kbuild: Do not reference *-n variables in the Makefile kbuild: simplify build, clean, modbuiltin shorthands kbuild: arm: Do not define "comma" twice kbuild: remove obj-n and lib-n handling kbuild: remove unnecessary variable initializaions kbuild: remove unnecessary "obj- := dummy.o" trick kbuild: handle C=... and M=... after entering into build directory kbuild: use $(Q) for sub-make target kbuild: fake the "Entering directory ..." message more simply kconfig/lxdialog: get ncurses CFLAGS with pkg-config kconfig: nconfig: fix multi-byte UTF handling kconfig: lxdialog: fix spelling kbuild: Make scripts executable kbuild: remove redundant clean-files from scripts/kconfig/Makefile kbuild: refactor script/kconfig/Makefile kbuild: handle the dependency of multi-objs hostprogs appropriately kbuild: handle multi-objs dependency appropriately
| * | kbuild: remove unnecessary "obj- := dummy.o" trickMasahiro Yamada2014-10-021-2/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | In these Makefiles, at least one of "obj-y" and "obj-" is non-empty, hence built-in.o is always created without such a trick. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Peter Foley <pefoley2@pefoley.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> [shmobile] Acked-by: David S. Miller <davem@davemloft.net> [networking] Signed-off-by: Michal Marek <mmarek@suse.cz>
* / clk: shmobile: Add r8a7794 supportHisashi Nakamura2014-08-271-0/+1
|/ | | | | | Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* clk: shmobile: Add R8A7740-specific clock supportUlrich Hecht2014-05-232-0/+200
| | | | | | | | | | Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: mstp: Fix the is_enabled() operationLaurent Pinchart2014-05-231-1/+1
| | | | | | | | | The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: r8a7779: Add clocks supportSimon Horman2014-05-132-0/+181
| | | | | | | | | | | | | The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: clk-mstp: change to using clock-indicesBen Dooks2014-05-131-2/+7
| | | | | | | | | | | | | | With the addition of clock-indices, we need to change the renesas clock implementation to use these instead of the local definition of "renesas,clock-indices". Since this will break booting with older device trees, we add a simple auto-detection of which properties are present. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-for-linus-3.15' of ↵Linus Torvalds2014-04-065-6/+110
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework changes from Mike Turquette: "The clock framework changes for 3.15 look similar to past pull requests. Mostly clock driver updates, more Device Tree support in the form of common functions useful across platforms and a handful of features and fixes to the framework core" * tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: shmobile: fix setting paretn clock rate clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 clk: Fix minor errors in of_clk_init() function comments clk: reverse default clk provider initialization order in of_clk_init() clk: sirf: update copyright years to 2014 clk: mmp: try to use closer one when do round rate clk: mmp: fix the wrong calculation formula clk: mmp: fix wrong mask when calculate denominator clk: st: Adds quadfs clock binding clk: st: Adds clockgen-vcc and clockgen-mux clock binding clk: st: Adds clockgen clock binding clk: st: Adds divmux and prediv clock binding clk: st: Support for A9 MUX clocks clk: st: Support for ClockGenA9/DDR/GPU clk: st: Support for QUADFS inside ClockGenB/C/D/E/F clk: st: Support for VCC-mux and MUX clocks clk: st: Support for PLLs inside ClockGenA(s) clk: st: Support for DIVMUX and PreDiv Clocks clk: support hardware-specific debugfs entries clk: s2mps11: Use of_get_child_by_name ...
| * clk: shmobile: fix setting paretn clock rateBen Dooks2014-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | If the driver needs to change a clock rate, then it must be propogated through the MSTP clock to the parent clock (such as shdi0 -> sd0). Without this we cannot up-rate default clocks which are really slow (such as the mmcif1 which defaults to 12MHz where it could be running at 97MHz) Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1Ben Dooks2014-04-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks parented to pll1_div2 where the hardware diagram shows these to be directly fed from pll1. This fixes the initial rate for sdh0 clock to be 97.5MHz instead of the reported 48MHz where the manual says the default register values are for 97.5MHz. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: shmobile: add CPG driver for rz-platformsWolfram Sang2014-03-212-0/+104
| | | | | | | | | | Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: shmobile: div6: use proper description in kernel docWolfram Sang2014-02-251-1/+1
| | | | | | | | | | | | | | | | | | These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2014-03-081-2/+34
|\ \ | |/ |/| | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk driver fix from Mike Turquette: "Single fix for a clock driver merged in 3.14-rc1. Without this fix the CPU frequency cannot be scaled" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change
| * clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency changeBenoit Cousson2014-03-061-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart2014-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocksLaurent Pinchart2014-02-191-1/+9
|/ | | | | | | | | | | The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: Fix MSTP clock array initializationValentine Barshak2014-01-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clks member of the clk_onecell_data structure should point to a valid clk array (no NULL entries allowed), and the clk_num should be equal to the number of elements in the clks array. The MSTP driver fails to satisfy the above conditions. The clks array may contain NULL entries if not all clock-indices are initialized in the device tree. Thus, if the clock indices are interleaved we end up with NULL pointers in-between. The other problem is the driver uses maximum clock index as the number of clocks, which is incorrect (less than the actual number of clocks by 1). Fix the first issue by pre-setting the whole clks array with ERR_PTR(-ENOENT) pointers instead of zeros; and use maximum clkidx + 1 as the number of clocks to fix the other one. This should make of_clk_src_onecell_get() return the following: * valid clk pointers for all clocks registered; * ERR_PTR(-EINVAL) if (idx >= clk_data->clk_num); * ERR_PTR(-ENOENT) if the clock at the selected index was not initialized in the device tree (and was not registered). Changes in V2: * removed brackets from the one-line for loop Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: Fix MSTP clock indexValentine Barshak2014-01-141-2/+2
| | | | | | | | | | | | | | | | | Use clkidx when registering MSTP clocks instead of loop counter since the value is then used to access the specific clock index bit in the mstp register. The issue was introduced by the following commit: f94859c215b6d977 "clk: shmobile: Add MSTP clock support" Changes in V2: * none Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: emev2: Add support for emev2 SMU clocks with DTTakashi Yoshii2013-12-142-1/+105
| | | | | | | | | | | | | | | | | | | | Device tree clock binding document for EMMA Mobile EV2 SMU, And Common clock framework based implementation of it. Following nodes are defined to describe clock tree. - renesas,emev2-smu - renesas,emev2-smu-clkdiv - renesas,emev2-smu-gclk These bindings are designed manually based on 19UH0037EJ1000_SMU : System Management Unit User's Manual So far, reparent is not implemented, and is fixed to index #0. Clock tree description is not included, and should be provided by device-tree. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* clk: shmobile: Add MSTP clock supportLaurent Pinchart2013-12-132-0/+230
| | | | | | | | | | MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: Add DIV6 clock supportLaurent Pinchart2013-12-132-0/+186
| | | | | | | | | | | DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: Add R-Car Gen2 clocks supportLaurent Pinchart2013-12-132-0/+303
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are too custom to be supported in a generic driver. Those clocks can be divided in two categories: - Fixed rate clocks with multiplier and divisor set according to boot mode configuration - Custom divider clocks with SoC-specific divider values This driver supports both. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 00:29:32 +0100