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path: root/drivers/clk/socfpga/clk-agilex.c (follow)
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* clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen2021-09-251-9/+0
* clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen2021-07-271-1/+1
* clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen2021-07-271-0/+9
* clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen2021-07-271-4/+4
* clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen2021-06-281-1/+3
* clk: agilex/stratix10: fix bypass representationDinh Nguyen2021-06-281-11/+46
* clk: agilex/stratix10: remove noc_clkDinh Nguyen2021-06-281-17/+15
* clk: socfpga: Fix code formattingStephen Boyd2021-03-311-1/+2
* clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen2021-03-311-54/+60
* clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen2021-02-121-2/+86
* clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing2020-09-221-13/+0
* clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen2020-06-201-1/+1
* clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen2020-06-201-1/+5
* clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen2020-05-271-0/+454