| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: agilex/stratix10/n5x: fix how the bypass_reg is handled | Dinh Nguyen | 2021-06-28 | 1 | -3/+8 |
| * | clk: socfpga: Convert to s10/agilex/n5x to use clk_hw | Dinh Nguyen | 2021-03-31 | 1 | -18/+24 |
| * | clk: socfpga: agilex: add clock driver for eASIC N5X platform | Dinh Nguyen | 2021-02-12 | 1 | -0/+53 |
| * | clk: socfpga: stratix10: use new parent data scheme | Dinh Nguyen | 2020-05-27 | 1 | -4/+6 |
| * | clk: socfpga: stratix10: simplify parameter passing | Dinh Nguyen | 2020-02-13 | 1 | -21/+21 |
| * | clk: socfpga: stratix10: fix rate caclulationg for cnt_clks | Dinh Nguyen | 2019-08-14 | 1 | -1/+1 |
| * | clk: Remove io.h from clk-provider.h | Stephen Boyd | 2019-05-15 | 1 | -0/+1 |
| * | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen | 2018-04-06 | 1 | -0/+149 |
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