| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: socfpga: Convert to s10/agilex/n5x to use clk_hw | Dinh Nguyen | 2021-03-31 | 1 | -12/+12 |
| * | clk: socfpga: agilex: add clock driver for eASIC N5X platform | Dinh Nguyen | 2021-02-12 | 1 | -1/+16 |
| * | clk: socfpga: agilex: add clock driver for the Agilex platform | Dinh Nguyen | 2020-05-27 | 1 | -0/+2 |
| * | clk: socfpga: stratix10: use new parent data scheme | Dinh Nguyen | 2020-05-27 | 1 | -4/+4 |
| * | clk: socfpga: stratix10: simplify parameter passing | Dinh Nguyen | 2020-02-13 | 1 | -17/+8 |
| * | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen | 2018-04-06 | 1 | -0/+80 |
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