| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks | Vipul Kumar Samar | 2012-11-21 | 1 | -1/+2 |
| * | Viresh has moved | Viresh Kumar | 2012-06-20 | 1 | -1/+1 |
| * | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+198 |
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