Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | CLK: SPEAr: Update clock rate table | Deepak Sikri | 2012-11-21 | 1 | -21/+68 |
* | CLK: SPEAr: Add missing clocks | Vipul Kumar Samar | 2012-11-21 | 1 | -0/+4 |
* | CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks | Vipul Kumar Samar | 2012-11-21 | 1 | -36/+37 |
* | CLK: SPEAr13xx: fix parent names of multiple clocks | Shiraz Hashim | 2012-11-21 | 1 | -3/+3 |
* | CLK: SPEAr13xx: Fix mux clock names | Shiraz Hashim | 2012-11-21 | 1 | -10/+10 |
* | CLK: SPEAr: Fix dev_id & con_id for multiple clocks | Rajeev Kumar | 2012-11-21 | 1 | -20/+22 |
* | Clk: SPEAr1340: Update sys clock parent array | Vipul Kumar Samar | 2012-07-18 | 1 | -2/+2 |
* | clk: SPEAr1340: Fix clk enable register for uart1 and i2c1. | Vipul Kumar Samar | 2012-07-18 | 1 | -2/+2 |
* | clk:spear1340:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 2012-07-18 | 1 | -138/+135 |
* | Viresh has moved | Viresh Kumar | 2012-06-20 | 1 | -1/+1 |
* | SPEAr13xx: Add common clock framework support | Viresh Kumar | 2012-05-14 | 1 | -0/+964 |