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* Clk: SPEAr1340: Update sys clock parent arrayVipul Kumar Samar2012-07-181-2/+2
* clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.Vipul Kumar Samar2012-07-181-2/+2
* Clk:spear6xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar2012-07-181-62/+60
* Clk:spear3xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar2012-07-181-94/+86
* clk:spear1310:Fix: Rename clk ids within predefined limitVipul Kumar Samar2012-07-181-157/+155
* clk:spear1340:Fix: Rename clk ids within predefined limitVipul Kumar Samar2012-07-181-138/+135
* clk: SPEAr600: Fix ethernet clock name for DT based probingStefan Roese2012-06-261-1/+1
* Viresh has movedViresh Kumar2012-06-2010-10/+10
* SPEAr13xx: Add common clock framework supportViresh Kumar2012-05-143-0/+2072
* SPEAr: Switch to common clock frameworkViresh Kumar2012-05-123-0/+957
* SPEAr: clk: Add General Purpose Timer Synthesizer clockViresh Kumar2012-05-123-1/+172
* SPEAr: clk: Add Fractional Synthesizer clockViresh Kumar2012-05-123-1/+182
* SPEAr: clk: Add Auxiliary Synthesizer clockViresh Kumar2012-05-123-1/+242
* SPEAr: clk: Add VCO-PLL Synthesizer clockViresh Kumar2012-05-124-0/+462