Commit message (Expand) | Author | Age | Files | Lines | ||
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* | clk:spear1340:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 2012-07-18 | 1 | -138/+135 | |
* | clk: SPEAr600: Fix ethernet clock name for DT based probing | Stefan Roese | 2012-06-26 | 1 | -1/+1 | |
* | Viresh has moved | Viresh Kumar | 2012-06-20 | 10 | -10/+10 | |
* | SPEAr13xx: Add common clock framework support | Viresh Kumar | 2012-05-14 | 3 | -0/+2072 | |
* | SPEAr: Switch to common clock framework | Viresh Kumar | 2012-05-12 | 3 | -0/+957 | |
* | SPEAr: clk: Add General Purpose Timer Synthesizer clock | Viresh Kumar | 2012-05-12 | 3 | -1/+172 | |
* | SPEAr: clk: Add Fractional Synthesizer clock | Viresh Kumar | 2012-05-12 | 3 | -1/+182 | |
* | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar | 2012-05-12 | 3 | -1/+242 | |
* | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 2012-05-12 | 4 | -0/+462 |