| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sprd: add clocks support for SC9860 | Chunyan Zhang | 2017-12-22 | 1 | -0/+3 |
| * | clk: sprd: add adjustable pll support | Chunyan Zhang | 2017-12-22 | 1 | -0/+1 |
| * | clk: sprd: add composite clock support | Chunyan Zhang | 2017-12-22 | 1 | -0/+1 |
| * | clk: sprd: add divider clock support | Chunyan Zhang | 2017-12-22 | 1 | -0/+1 |
| * | clk: sprd: add mux clock support | Chunyan Zhang | 2017-12-22 | 1 | -0/+1 |
| * | clk: sprd: add gate clock support | Chunyan Zhang | 2017-12-22 | 1 | -0/+1 |
| * | clk: sprd: Add common infrastructure | Chunyan Zhang | 2017-12-22 | 1 | -0/+3 |
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