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path: root/drivers/clk/sprd (follow)
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* clk: sprd: don't gate uart console clockChunyan Zhang2020-04-131-1/+2
* clk: sprd: fix to get a correct ibias of pllChunyan Zhang2020-04-031-3/+4
* clk: sprd: add clocks support for SC9863AChunyan Zhang2020-03-253-0/+1781
* clk: sprd: support to get regmap from parent nodeChunyan Zhang2020-03-251-1/+9
* clk: sprd: Add macros for referencing parents without stringsChunyan Zhang2020-03-255-55/+196
* clk: sprd: add gate for pll clocksXiaolong Zhang2020-03-252-2/+36
*-. Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and ...Stephen Boyd2019-11-271-1/+1
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| | * clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_...Baolin Wang2019-11-131-1/+1
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* / clk: sprd: Change to use devm_platform_ioremap_resource()Baolin Wang2019-10-171-3/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-09-212-2/+5
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| *-. Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-nextStephen Boyd2019-09-201-0/+2
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| | | * clk: sprd: add missing kfreeChunyan Zhang2019-09-181-0/+2
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| * / clk: sprd: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
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* / clk: sprd: Select REGMAP_MMIO to avoid compile errorsChunyan Zhang2019-07-221-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-172-3/+11
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| * clk: sprd: Add check for return value of sprd_clk_regmap_init()Chunyan Zhang2019-06-281-1/+4
| * clk: sprd: Check error only for devm_regmap_init_mmio()Chunyan Zhang2019-06-261-1/+1
| * clk: sprd: Switch from of_iomap() to devm_ioremap_resource()Chunyan Zhang2019-06-261-1/+6
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
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* clk: sprd: Use the correct style for SPDX License IdentifierNishad Kamdar2019-05-016-6/+6
* clk: sprd: add RTC gate for SC9860Chunyan Zhang2018-03-161-0/+76
* Merge branch 'clk-divider-container' into clk-nextStephen Boyd2018-01-271-1/+2
* clk: sprd: add clocks support for SC9860Chunyan Zhang2017-12-223-0/+1987
* clk: sprd: add adjustable pll supportChunyan Zhang2017-12-223-0/+375
* clk: sprd: add composite clock supportChunyan Zhang2017-12-223-0/+112
* clk: sprd: add divider clock supportChunyan Zhang2017-12-223-0/+166
* clk: sprd: add mux clock supportChunyan Zhang2017-12-223-0/+151
* clk: sprd: add gate clock supportChunyan Zhang2017-12-223-0/+171
* clk: sprd: Add common infrastructureChunyan Zhang2017-12-224-0/+141