| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | drivers: clk: st: PLL rate change implementation for DVFS | Gabriel Fernandez | 2015-10-09 | 1 | -0/+2 |
| * | clk: st: Support for PLLs inside ClockGenA(s) | Gabriel FERNANDEZ | 2014-03-25 | 1 | -0/+48 |
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