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* drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez2015-10-091-0/+194
* drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez2015-10-093-10/+216
* drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez2015-10-091-1/+59
* clk: st: fix handling result of of_property_count_stringsAndrzej Hajda2015-10-021-3/+4
* drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez2015-09-172-10/+10
* clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-254-16/+16
* clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd2015-08-251-1/+1
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-284-0/+4
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| * clk: st: Include clk.hStephen Boyd2015-07-204-0/+4
* | clk: st: make use of of_clk_parent_fill helper functionDinh Nguyen2015-07-282-9/+4
* | clk: st: Fix error paths and allocation styleStephen Boyd2015-07-141-38/+45
* | drivers: clk: st: Incorrect register offset used for lock_statusPankaj Dev2015-07-081-1/+1
* | drivers: clk: st: Fix mux bit-setting for Cortex A9 clocksGabriel Fernandez2015-07-061-1/+1
* | drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev2015-07-064-6/+8
* | drivers: clk: st: Fix flexgen lock initGiuseppe Cavallaro2015-07-061-0/+2
* | drivers: clk: st: Fix FSYN channel valuesGabriel Fernandez2015-07-061-2/+2
* | drivers: clk: st: Remove unused codeGabriel Fernandez2015-07-061-4/+0
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* clk: st: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-042-2/+2
* clk: st: Silence sparse warningsStephen Boyd2015-05-154-17/+17
* clk: constify of_device_id arrayFabian Frederick2015-04-013-7/+7
* clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas2015-02-182-17/+17
* clk: st: STiH410: Fix pdiv and fdiv divisor when setting ratePeter Griffin2015-01-201-4/+15
* clk: st: Use round to closest divider flagGabriel FERNANDEZ2014-07-291-1/+2
* clk: st: Update frequency tables for fs660c32 and fs432c65Gabriel FERNANDEZ2014-07-291-8/+59
* clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ2014-07-291-0/+16
* clk: st: STiH407: Support for clockgenD0/D2/D3Gabriel FERNANDEZ2014-07-291-0/+46
* clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ2014-07-292-0/+83
* clk: st: Add quadfs reset handlingGabriel FERNANDEZ2014-07-291-0/+5
* clk: st: Add polarity bit indicationGabriel FERNANDEZ2014-07-291-5/+7
* clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ2014-07-291-0/+16
* clk: st: STiH407: Support for A9 MUX ClocksGabriel FERNANDEZ2014-07-291-0/+9
* clk: st: STiH407: Support for Flexgen ClocksGabriel FERNANDEZ2014-07-292-1/+332
* clk: st: Remove uncessary (void *) castGabriel FERNANDEZ2014-07-291-4/+4
* clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ2014-07-291-16/+14
* clk: st: use static const for stm_fs tablesGabriel FERNANDEZ2014-07-291-17/+17
* clk: st: Terminate of match tableStephen Boyd2014-05-281-0/+1
* clk: st: Fix memory leakValentin Ilie2014-05-241-1/+3
* clk: st: Support for A9 MUX clocksGabriel FERNANDEZ2014-03-251-0/+19
* clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ2014-03-251-0/+139
* clk: st: Support for QUADFS inside ClockGenB/C/D/E/FGabriel FERNANDEZ2014-03-252-1/+1040
* clk: st: Support for VCC-mux and MUX clocksGabriel FERNANDEZ2014-03-251-0/+272
* clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ2014-03-253-1/+608
* clk: st: Support for DIVMUX and PreDiv ClocksGabriel FERNANDEZ2014-03-252-0/+530
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