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path: root/drivers/clk/st (follow)
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-302-12/+2
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: st: Remove usage of CLK_IS_BASICStephen Boyd2018-12-103-4/+4
* clk: Convert to using %pOFn instead of device_node.nameRob Herring2018-08-301-1/+1
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-132-2/+2
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* clk: st: clk-flexgen: Unmap region obtained by of_iomapArvind Yadav2016-12-091-1/+4
* drivers: clk: st: Handle clk synchronous mode for video clocksGabriel Fernandez2016-09-171-2/+35
* drivers: clk: st: Add clock propagation for audio clocksGabriel Fernandez2016-09-171-1/+25
* drivers: clk: st: Add fs660c32 synthesizer algorithmGabriel Fernandez2016-09-171-69/+111
* drivers: clk: st: Simplify clock binding of STiH4xx platformsGabriel Fernandez2016-09-173-77/+55
* drivers: clk: st: Remove stih415-416 clock supportGabriel Fernandez2016-09-173-1404/+1
* clk: st: clkgen-pll: Detect critical clocksLee Jones2016-06-301-10/+17
* clk: st: clkgen-fsyn: Detect critical clocksLee Jones2016-06-301-3/+7
* clk: st: clk-flexgen: Detect critical clocksLee Jones2016-06-301-1/+3
* clk: st: Remove impossible check for of_clk_get_parent_count() < 0Stephen Boyd2016-02-272-4/+4
* clk: st: avoid uninitialized variable useArnd Bergmann2016-01-301-2/+6
* clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2016-01-291-5/+4
* clk: st: avoid uninitialized variable useArnd Bergmann2015-11-201-8/+9
* drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez2015-10-091-0/+194
* drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez2015-10-093-10/+216
* drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez2015-10-091-1/+59
* clk: st: fix handling result of of_property_count_stringsAndrzej Hajda2015-10-021-3/+4
* drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez2015-09-172-10/+10
* clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-254-16/+16
* clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd2015-08-251-1/+1
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-284-0/+4
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| * clk: st: Include clk.hStephen Boyd2015-07-204-0/+4
* | clk: st: make use of of_clk_parent_fill helper functionDinh Nguyen2015-07-282-9/+4
* | clk: st: Fix error paths and allocation styleStephen Boyd2015-07-141-38/+45
* | drivers: clk: st: Incorrect register offset used for lock_statusPankaj Dev2015-07-081-1/+1
* | drivers: clk: st: Fix mux bit-setting for Cortex A9 clocksGabriel Fernandez2015-07-061-1/+1
* | drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev2015-07-064-6/+8
* | drivers: clk: st: Fix flexgen lock initGiuseppe Cavallaro2015-07-061-0/+2
* | drivers: clk: st: Fix FSYN channel valuesGabriel Fernandez2015-07-061-2/+2
* | drivers: clk: st: Remove unused codeGabriel Fernandez2015-07-061-4/+0
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* clk: st: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-042-2/+2
* clk: st: Silence sparse warningsStephen Boyd2015-05-154-17/+17
* clk: constify of_device_id arrayFabian Frederick2015-04-013-7/+7
* clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas2015-02-182-17/+17
* clk: st: STiH410: Fix pdiv and fdiv divisor when setting ratePeter Griffin2015-01-201-4/+15
* clk: st: Use round to closest divider flagGabriel FERNANDEZ2014-07-291-1/+2
* clk: st: Update frequency tables for fs660c32 and fs432c65Gabriel FERNANDEZ2014-07-291-8/+59
* clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ2014-07-291-0/+16
* clk: st: STiH407: Support for clockgenD0/D2/D3Gabriel FERNANDEZ2014-07-291-0/+46
* clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ2014-07-292-0/+83
* clk: st: Add quadfs reset handlingGabriel FERNANDEZ2014-07-291-0/+5
* clk: st: Add polarity bit indicationGabriel FERNANDEZ2014-07-291-5/+7
* clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ2014-07-291-0/+16
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