| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sunxi-ng: a64: Allow parent change for VE clock | Jernej Skrabec | 2018-12-10 | 1 | -1/+1 |
| * | clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 2018-11-23 | 1 | -13/+24 |
| * | clk: sunxi-ng: a64: Fix gate bit of DSI DPHY | Jagan Teki | 2018-11-13 | 1 | -1/+1 |
| * | clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock | Icenowy Zheng | 2018-11-05 | 1 | -1/+6 |
| * | clk: sunxi-ng: a64: Add max. rate constraint to video PLLs | Icenowy Zheng | 2018-09-05 | 1 | -24/+26 |
| * | clk: sunxi-ng: a64: Add minimal rate for video PLLs | Jagan Teki | 2018-09-05 | 1 | -22/+24 |
| * | clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks | Chen-Yu Tsai | 2017-12-07 | 1 | -20/+37 |
| * | clk: sunxi-ng: Support multiple variable pre-dividers | Chen-Yu Tsai | 2017-06-07 | 1 | -5/+5 |
| * | clk: sunxi-ng: Fix div/mult settings for osc12M on A64 | Philipp Tomsich | 2017-03-20 | 1 | -1/+1 |
| * | clk: sunxi-ng: Mark structs static and cleanup spaces | Stephen Boyd | 2016-11-16 | 1 | -6/+6 |
| * | clk: sunxi-ng: Add A64 clocks | Maxime Ripard | 2016-11-03 | 1 | -0/+915 |
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