| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sunxi-ng: h6: Set video PLLs limits | Jernej Skrabec | 2018-11-05 | 1 | -0/+4 |
| * | clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width | Jagan Teki | 2018-11-05 | 1 | -3/+3 |
| * | clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks | Icenowy Zheng | 2018-09-05 | 1 | -20/+23 |
| * | clk: sunxi-ng: h6: fix PWM gate/reset offset | Rongyi Chen | 2018-08-27 | 1 | -1/+1 |
| * | clk: sunxi-ng: h6: fix bus clocks' divider position | Icenowy Zheng | 2018-08-27 | 1 | -4/+4 |
| * | clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU | Icenowy Zheng | 2018-03-21 | 1 | -0/+4 |
| * | clk: sunxi-ng: add support for the Allwinner H6 CCU | Icenowy Zheng | 2018-03-18 | 1 | -0/+1207 |
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