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path: root/drivers/clk/sunxi-ng/ccu-sun6i-a31.c (follow)
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-14/+25
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| * clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai2019-06-181-14/+25
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner2019-06-051-9/+1
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara2019-01-281-2/+2
* clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai2018-02-191-3/+3
* clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLLChen-Yu Tsai2017-10-131-13/+25
* clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collisionChen-Yu Tsai2017-09-291-1/+1
* clk: Convert to using %pOF instead of full_nameRob Herring2017-07-221-2/+1
* clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai2017-06-071-5/+5
* clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offsetChen-Yu Tsai2017-05-141-1/+1
* clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai2017-03-061-1/+1
* clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-021-2/+2
* clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai2016-11-211-1/+1
* clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai2016-10-191-0/+12
* clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clkChen-Yu Tsai2016-09-171-1/+1
* clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai2016-09-171-10/+10
* clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai2016-09-171-9/+13
* clk: sunxi-ng: Add A31/A31s clocksChen-Yu Tsai2016-08-251-0/+1235