| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock | Chen-Yu Tsai | 2017-03-06 | 1 | -1/+1 |
| * | clk: sunxi-ng: A31: Fix spdif clock register | Marcus Cooper | 2017-01-02 | 1 | -2/+2 |
| * | clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it | Chen-Yu Tsai | 2016-11-21 | 1 | -1/+1 |
| * | clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent | Chen-Yu Tsai | 2016-10-19 | 1 | -0/+12 |
| * | clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk | Chen-Yu Tsai | 2016-09-17 | 1 | -1/+1 |
| * | clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs | Chen-Yu Tsai | 2016-09-17 | 1 | -10/+10 |
| * | clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks | Chen-Yu Tsai | 2016-09-17 | 1 | -9/+13 |
| * | clk: sunxi-ng: Add A31/A31s clocks | Chen-Yu Tsai | 2016-08-25 | 1 | -0/+1235 |
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