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path: root/drivers/clk/sunxi-ng (follow)
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*-. Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', '...Stephen Boyd2019-03-081-1/+1
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| | * clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai2019-01-251-1/+1
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* | clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara2019-01-281-2/+2
* | clk: sunxi-ng: v3s: Fix TCON reset de-assert bitPaul Kocialkowski2019-01-221-1/+1
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* clk: sunxi-ng: a64: Allow parent change for VE clockJernej Skrabec2018-12-101-1/+1
* clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai2018-12-051-3/+3
* clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLLChen-Yu Tsai2018-12-051-13/+24
* clk: sunxi-ng: h3: Allow parent change for ve clockJernej Skrabec2018-12-041-1/+1
* clk: sunxi-ng: add support for suniv F1C100s SoCMesih Kilinc2018-12-044-0/+581
* clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai2018-12-031-1/+1
* clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC outputChen-Yu Tsai2018-11-301-0/+11
* clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLLChen-Yu Tsai2018-11-231-13/+24
* clk: sunxi-ng: a64: Fix gate bit of DSI DPHYJagan Teki2018-11-131-1/+1
* clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50IJagan Teki2018-11-131-0/+1
* clk: sunxi-ng: Add support for H6 DE3 clocksJernej Skrabec2018-11-052-4/+71
* clk: sunxi-ng: h6: Set video PLLs limitsJernej Skrabec2018-11-051-0/+4
* clk: sunxi-ng: Use u64 for calculation of NM rateJernej Skrabec2018-11-051-3/+15
* clk: sunxi-ng: Adjust MP clock parent rate when allowedJernej Skrabec2018-11-051-2/+62
* clk: sunxi-ng: sun50i: h6: Fix MMC clock mux widthJagan Teki2018-11-051-3/+3
* clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clockIcenowy Zheng2018-11-051-1/+6
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-10-3110-86/+143
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| * dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macroJagan Teki2018-09-051-1/+3
| * clk: sunxi-ng: a64: Add max. rate constraint to video PLLsIcenowy Zheng2018-09-051-24/+26
| * clk: sunxi-ng: a64: Add minimal rate for video PLLsJagan Teki2018-09-051-22/+24
| * clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocksIcenowy Zheng2018-09-051-20/+23
| * clk: sunxi-ng: a83t: Add max. rate constraint to video PLLsJernej Skrabec2018-08-271-0/+2
| * clk: sunxi-ng: nkmp: Add constraint for maximum rateJernej Skrabec2018-08-272-0/+8
| * clk: sunxi-ng: r40: Add max. rate constraint to video PLLsJernej Skrabec2018-08-271-26/+26
| * clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-videoJernej Skrabec2018-08-271-12/+13
| * clk: sunxi-ng: Add maximum rate constraint to NM PLLsJernej Skrabec2018-08-272-0/+37
| * clk: sunxi-ng: h6: fix PWM gate/reset offsetRongyi Chen2018-08-271-1/+1
| * clk: sunxi-ng: h6: fix bus clocks' divider positionIcenowy Zheng2018-08-271-4/+4
* | clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest settingChen-Yu Tsai2018-09-071-1/+9
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-08-163-35/+42
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| * clk: sunxi-ng: add A64 compatible stringIcenowy Zheng2018-06-271-7/+4
| * clk: sunxi-ng: r40: Export video PLLsJernej Skrabec2018-06-271-2/+6
| * clk: sunxi-ng: r40: Allow setting parent rate to display related clocksJernej Skrabec2018-06-271-4/+8
| * clk: sunxi-ng: r40: Add minimal rate for video PLLsJernej Skrabec2018-06-271-22/+24
* | clk: sunxi-ng: replace lib-y with obj-yMasahiro Yamada2018-06-211-24/+15
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* clk: sunxi-ng: r40: export a regmap to access the GMAC registerIcenowy Zheng2018-05-171-0/+33
* clk: sunxi-ng: r40: rewrite init code to a platform driverIcenowy Zheng2018-05-171-11/+28
* clk: sunxi-ng: add support for H6 PRCM CCUIcenowy Zheng2018-05-044-0/+232
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-04-1410-35/+1375
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| * clk: sunxi-ng: add missing hdmi-slow clock for H6 CCUIcenowy Zheng2018-03-212-1/+5
| * clk: sunxi-ng: add support for the Allwinner H6 CCUIcenowy Zheng2018-03-184-0/+1269
| * clk: sunxi-ng: Support fixed post-dividers on NKMP style clocksIcenowy Zheng2018-03-182-3/+19
| * clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEOJernej Skrabec2018-03-021-1/+3
| * clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec2018-03-021-3/+6
| * clk: sunxi-ng: h3: h5: Add minimal rate for video PLLJernej Skrabec2018-03-021-11/+12
| * clk: sunxi-ng: Add check for minimal rate to NM PLLsJernej Skrabec2018-03-022-0/+34
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