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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-05-1017-53/+710
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| * Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd2017-04-227-18/+17
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| | * clk: sunxi-ng: a80: Fix audio PLL comment not matching actual codeChen-Yu Tsai2017-04-131-2/+1
| | * clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatchChen-Yu Tsai2017-04-132-3/+3
| | * clk: sunxi-ng: use 1 as fallback for minimum multiplierChen-Yu Tsai2017-04-134-11/+11
| | * clk: sunxi-ng: fix PRCM CCU CLK_NUMBER valueIcenowy Zheng2017-04-101-1/+1
| | * clk: sunxi-ng: fix PRCM CCU ir clk parentIcenowy Zheng2017-04-101-1/+1
| * | Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-04-1913-37/+695
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| | * clk: sunxi-ng: Display index when clock registration failsPriit Laes2017-04-061-2/+2
| | * clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorChen-Yu Tsai2017-04-051-7/+11
| | * clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocksChen-Yu Tsai2017-04-051-18/+52
| | * clk: sunxi-ng: mult: Support PLL lock detectionChen-Yu Tsai2017-04-052-0/+4
| | * clk: sunxi-ng: add support for PRCM CCUsIcenowy Zheng2017-04-044-0/+247
| | * clk: sunxi-ng: sun5i: Fix mux width for csi clockPriit Laes2017-03-061-1/+1
| | * clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCsPeter Robinson2017-03-061-0/+8
| | * clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng2017-03-063-9/+323
| | * clk: sunxi-ng: gate: Support common pre-dividersChen-Yu Tsai2017-03-061-0/+47
* | | clk: sunxi-ng: always select CCU_GATEArnd Bergmann2017-04-281-1/+1
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* | clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai2017-04-131-0/+11
* | clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocksChen-Yu Tsai2017-04-132-0/+61
* | clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driverTobias Regnery2017-04-131-0/+1
* | clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERTobias Regnery2017-04-131-0/+1
* | clk: sunxi-ng: fix recalc_rate formula of NKMP clocksIcenowy Zheng2017-03-201-1/+1
* | clk: sunxi-ng: Fix div/mult settings for osc12M on A64Philipp Tomsich2017-03-201-1/+1
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* clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai2017-03-061-1/+1
* clk: sunxi: ccu-sun5i needs nkmpArnd Bergmann2017-03-061-0/+1
* clk: sunxi-ng: mp: Adjust parent rate for pre-dividersChen-Yu Tsai2017-03-061-0/+8
* clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()Wei Yongjun2017-02-071-1/+1
* clk: sunxi-ng: select SUNXI_CCU_MULT for sun5iArnd Bergmann2017-02-061-0/+1
* clk: sunxi-ng: Check kzalloc() for errors and cleanup error pathStephen Boyd2017-02-061-0/+15
* clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai2017-01-303-0/+317
* clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai2017-01-303-0/+170
* clk: sunxi-ng: Add A80 CCUChen-Yu Tsai2017-01-304-0/+1291
* clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2017-01-302-2/+9
* clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai2017-01-301-1/+12
* clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai2017-01-301-0/+15
* clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai2017-01-301-3/+4
* clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard2017-01-271-1/+1
* clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard2017-01-271-0/+12
* clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard2017-01-234-0/+1100
* clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2017-01-232-1/+9
* clk: sunxi-ng: Implement multiplier maximumMaxime Ripard2017-01-236-20/+32
* clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard2017-01-231-1/+1
* clk: sunxi-ng: Implement factors offsetsMaxime Ripard2017-01-238-29/+79
* clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2017-01-232-0/+10
* clk: sunxi-ng: add support for V3s CCUIcenowy Zheng2017-01-204-0/+666
* clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand2017-01-171-1/+1
* clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-021-2/+2
* clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng2017-01-021-1/+1
* clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng2017-01-021-0/+10
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 06:37:30 +0100