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* Merge branch 'clk-fixes' into clk-nextMichael Turquette2016-07-222-5/+4
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| * clk: sunxi: remove unused variableArnd Bergmann2016-06-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The only use of the local num_parents variable was remove, so we now get a warning: drivers/clk/sunxi/clk-sun4i-tcon-ch1.c: In function 'tcon_ch1_get_parent': drivers/clk/sunxi/clk-sun4i-tcon-ch1.c:82:6: error: unused variable 'num_parents' [-Werror=unused-variable] This removes the variable. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 4de2d58bc973 ("clk: sunxi: tcon-ch1: Do not return a negative error in get_parent") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: display: Add per-clock flagsMaxime Ripard2016-06-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCON channel 0 clock that is the parent clock of our pixel clock is expected to change its rate depending on the resolution we want to output in our display engine. However, since it's only a mux, the only way it can do that is by changing its parents rate. Allow to give flags in our display clocks description, and add the CLK_SET_RATE_PARENT flag for the TCON channel 0 flag. Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: tcon-ch1: Do not return a negative error in get_parentMaxime Ripard2016-06-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | get_parent is supposed to return an unsigned 8 bit integer, so returning -EINVAL is a bad idea. Remove it. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: make clk-* explicitly non-modularPaul Gortmaker2016-07-076-65/+12
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have the following file --> Kconfig mapping: sunxi/clk-factors.c obj-y sunxi/clk-sun6i-apb0-gates.c CONFIG_MFD_SUN6I_PRCM (bool) sunxi/clk-sun6i-apb0.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun6i-ar100.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun8i-apb0.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun9i-mmc.c obj-y Hence none of these are being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get mostly the same changes, so they are handled in batch. Changes are (1) convert to builtin_platform_register, (2) use the init.h header, (3) delete the MODULE_LICENCE/MODULE_AUTHOR and associated tags, and (4) delete any ".remove" functions. There was a stray module.h in a file not using any init.h or module.h stuff, so we simply removed that one. In two cases, we explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. We delete the MODULE_LICENSE etc. tags since all that information is already contained at the top of each file in the comments. Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-9-paul.gortmaker@windriver.com
* clk: sunxi: Add display and TCON0 clocks driverMaxime Ripard2016-05-122-0/+262
| | | | | | | | | | | | | The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'sunxi-clocks-for-4.7' of ↵Stephen Boyd2016-05-036-13/+470
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent
| * clk: sunxi: Let divs clocks read the base factor clock name from devicetreeJens Kuske2016-04-251-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. [Andre: Make temporary name allocation dynamic.] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add TCON channel1 clockMaxime Ripard2016-04-222-0/+301
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: sunxi: Add PLL3 clockMaxime Ripard2016-04-222-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Use resource_sizeVaishali Thakkar2016-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | Use the function resource_size instaed of explicit computation. Problem found using Coccinelle. Signed-off-by: Vaishali Thakkar <vaishali.thakkar@oracle.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add sun6i/8i display supportJean-Francois Moine2016-04-221-0/+38
| | | | | | | | | | | | | | | | Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: mod1 clock should modify it's parentAndrea Venturi2016-04-221-1/+1
| | | | | | | | | | | | | | add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: Remove CLK_IS_ROOTStephen Boyd2016-04-161-2/+1
| | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: sunxi: Make reset_control_ops constPhilipp Zabel2016-03-303-3/+3
|/ | | | | | | | The sunxi_ve_reset_ops, sun9i_mmc_reset_ops, and sunxi_usb_reset_ops structures are never modified. Make them const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sunxi: Remove use of variable length arrayStephen Boyd2016-03-151-2/+9
| | | | | | | | | | | | Using an array allocated on the stack may lead to stack overflows and other problems so let's move the allocation to the heap instead. This silences the following checker warning as well. drivers/clk/sunxi/clk-sun8i-mbus.c:36:29: warning: Variable length array is used Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sunxi: Add apb0 gates for H3Krzysztof Adamski2016-02-251-0/+2
| | | | | | | | | | | | | | This patch adds support for APB0 in H3. It seems to be compatible with earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, etc). Since this gates behave just like any Allwinner clock gate, add a generic compatible that can be reused if we don't have any clock to protect. Signed-off-by: Krzysztof Adamski <k@japko.eu> [Maxime: Removed the H3 compatible from the simple-gates driver, reworked the commit log a bit] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Improve divs_clk error handling and reportingAndre Przywara2016-02-221-3/+15
| | | | | | | | | We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: improve divider_clk error handling and reportingAndre Przywara2016-02-221-3/+33
| | | | | | | | | | | We now report a failing ioremap, failing output names parsing, failures in table registration and in the final step. Also there was a bug where clk_register_divider_table() would return an ERR_PTR value instead of NULL, which we were checking for. We now implement proper rollback in case of an error. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: improve mux_clk error handling and reportingAndre Przywara2016-02-221-6/+15
| | | | | | | | | We now catch and report a failing ioremap, also a failure in the final step of the clock registration is now handled and reported. Also warnings are turned into errors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Fix sun8i-a23-apb0-clk divider flagsChen-Yu Tsai2016-02-161-1/+1
| | | | | | | | | | | | The APB0 clock on A23 is a zero-based divider, not a power-of-two based divider. Note that this patch does not apply cleanly to kernels before 4.5-rc1, which added CLK_OF_DECLARE support to this driver. Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Remove clk_register_clkdev callsMaxime Ripard2016-02-118-19/+4
| | | | | | | Now that our protection code doesn't use the global name lookup anymore, we can remove the clkdev registrations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Remove old probe and protection codeMaxime Ripard2016-02-111-108/+0
| | | | | | | Now that we don't have any user left for the old registration code, we can remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: convert current clocks registration to CLK_OF_DECLAREMaxime Ripard2016-02-111-17/+133
| | | | | | | | | | | | | | | | | The current clock registration and protection code has a few drawbacks, the two main ones being that we create a lot of orphans clock in the registration phase, which will be troublesome when we will start being less relaxed about them. The protection code also relies on clkdev, which we don't really use but for this particular case. Fix both at the same time by moving everyone to the CLK_OF_DECLARE that will probe our clock tree in the right and thus avoid orphans, and by protecting directly the clock returned by our registration function. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Make clocks setup functions take const pointerMaxime Ripard2016-02-111-3/+3
| | | | | | | | | | | | | All the data structure that we pass to the clocks setup functions are declared const, while our setup functions expects a regular pointer. This was hidden by the fact that we cast a void * pointer back to these structures, which made it go unnoticed. Fix the functions prototype. Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Make clocks setup functions return their clockMaxime Ripard2016-02-111-7/+10
| | | | | | | | | | | The clocks registration code in clk-sunxi was most of the time not returning the struct clk (or struct clk array) that was registered, preventing the users of such functions to manipulate it, for example to protect it. Make them return it so that we can start using it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: improve error reporting for the mux clockAndre Przywara2016-02-021-4/+16
| | | | | | | | | | | | clk_register_mux returns a pointer wrapped error value in case of failure, so a simple NULL check is not sufficient to catch errors. Fix that and elaborate on the failure reason on the way. The whole function does not return any error value, so silently failing may leave users scratching their heads because the kernel does not provide any clues on what's wrong. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: don't mark sun6i_ar100_data __initconstArnd Bergmann2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | The clk-sun6i-ar100 clk driver is a platform driver that may use deferred probing, so its probe function must not access __init symbols. Kbuild warns about this: WARNING: drivers/clk/sunxi/built-in.o(.text+0x15f0): Section mismatch in reference from the function sun6i_a31_ar100_clk_probe() to the (unknown reference) .init.rodata:(unknown) The function sun6i_a31_ar100_clk_probe() references the (unknown reference) __initconst (unknown). This is often because sun6i_a31_ar100_clk_probe lacks a __initconst annotation or the annotation of (unknown) is wrong. Removing the __initconst annotation avoids the warning and makes deferred probing work. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 3ca2377b6fed ("clk: sunxi: rewrite sun6i-ar100 using factors clk") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: add bus gates for A83TVishnu Patekar2016-02-021-0/+2
| | | | | | | | | | | | | | | | | | | A83T has similar bus gates that of H3, including single gating register has different clock parent. As per H3 and A83T datasheet, usbhost is under AHB2. However,below shows allwinner source code assignment: bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T. bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3 bits 29, 30, 31(ohci0,1,2) => AHB2 for H3. until, this confusion is cleared keep it H3 way. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Add apb0 gates for A83TVishnu Patekar2016-02-021-0/+2
| | | | | | | | | | | APB0 is part of PRCM, and is compatible with earlier SOCs. apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks. This patch adds support for APB0 gates for A83T. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clkChen-Yu Tsai2016-01-291-45/+76
| | | | | | | | | | | sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very complicated clocks, but is not really needed here. Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux + divider. This makes the code easier to understand. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: rewrite sun6i-ar100 using factors clkChen-Yu Tsai2016-01-291-174/+61
| | | | | | | | | sun6i's AR100 clock is a classic factors clk case: AR100 = ((parent mux) >> p) / (m + 1) Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalcChen-Yu Tsai2016-01-291-208/+83
| | | | | | | | | The factors clk implementation has been extended to support custom recalc callbacks to support clocks that use one factor for certain parents only, like a pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Drop round_rate from clk opsChen-Yu Tsai2016-01-291-16/+0
| | | | | | | | | | The common clock framework requires either determine_rate or round_rate to be implemented. We use determine_rate so we can pass the parent index to the get_factors callback. This cannot be done easily with round_rate, so just drop it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Support custom formulasChen-Yu Tsai2016-01-292-2/+32
| | | | | | | | | | | | Some clocks cannot be modelled using the standard factors clk formula, such as clocks with special pre-dividers on one parent, or clocks with all power-of-two dividers. Add support for a custom .recalc callback for factors clk. Also pass the current parent index to the .get_factor and .recalc callbacks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Consolidate get_factors parameters into a structChen-Yu Tsai2016-01-276-219/+155
| | | | | | | | | | | | | | The .get_factors callback of factors_clk has 6 parameters. To extend factors_clk in any way that requires adding parameters to .get_factors would make that list even longer, not to mention changing all the function declarations. Do this once now and consolidate all the parameters into a struct. Also drop the space before function pointer arguments, since checkpatch complains. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Add unregister functionChen-Yu Tsai2016-01-272-0/+30
| | | | | | | | | | | sunxi's factors clk did not have an unregister function. This means multiple structs were leaked whenever a factors clk was unregistered. Add an unregister function for it. Also keep pointers to the mux and gate structs so they can be freed. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Add clk cleanup in sunxi_factors_register() error pathChen-Yu Tsai2016-01-271-15/+29
| | | | | | | | sunxi_factors_register() does not check for failures or cleanup after clk_register_composite() or other clk-related calls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: factors: Make struct clk_factors_config table constChen-Yu Tsai2016-01-275-17/+17
| | | | | | | | | struct clk_factors_config contains shifts/widths for the factors of the factors clk. This is used to read out the factors from the register value. In no case is it written to, so make it const. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: usb: Sort clk providers by chip family and nameChen-Yu Tsai2016-01-251-12/+12
| | | | | | | | The latest addition of H3 USB clocks placed them at the bottom. Move it before A80 (sun9i), so they are sorted by SoC family then name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Drop clk.h includeStephen Boyd2016-01-241-1/+0
| | | | | | | | | | This file is a clock provider, not a clk consumer. Drop the clk.h include. Cc: Jens Kuske <jenskuske@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-clocks-for-4.5' of ↵Michael Turquette2015-12-248-12/+628
|\ | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.5 Clock patches for the Allwinner SoCs: - H3 clocks - A10/A20 Video Engine clocks - DRAM gates - A80 special CPU clock
| * clk: sunxi: fix handling return value of of_property_match_stringAndrzej Hajda2015-12-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The function can return negative values, so its result should be assigned to signed variable. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: signedness bug in sun8i_h3_bus_gates_init()Dan Carpenter2015-12-131-1/+1
| | | | | | | | | | | | | | | | "index" needs to be signed for the error handling to work. Fixes: ab6e23a4e388 ('clk: sunxi: Add H3 clocks support') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driverChen-Yu Tsai2015-12-092-12/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The APBS clock on sun9i is the same as the APB0 clock on sun8i. With sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE, instead of through a PRCM mfd device and subdevices for each clock and reset control. As such we need a CLK_OF_DECLARE version of the sun8i-a23-apb0-clk driver. Also, build it for sun9i/A80, and not just for configurations with MFD_SUN6I_PRCM enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]iChen-Yu Tsai2015-12-082-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | The video engine has its own special module clock, consisting of a clock gate, configurable dividers, and a reset control. On later (sun[68]i) families, the reset control is moved out of this piece of hardware and grouped with reset controls of other peripherals. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add H3 clocks supportJens Kuske2015-12-083-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H3 clock control unit is similar to the those of other sun8i family members like the A23. It adds a new bus gates clock similar to the simple gates, but with a different parent clock for each single gate. Some of the gates use the new AHB2 clock as parent, whose clock source is muxable between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add DRAM gates support for sun4i-a10Chen-Yu Tsai2015-12-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10/A20 share the same set of DRAM clock gates, which controls direct memory access for some peripherals. On the A10, bit 15 controls the system's DRAM clock output (possibly to the DRAM chips), which we need to keep on. On the A20 this has been moved to the DRAM controller, becoming a no-op. However it is still listed in the user manual, so add it anyway. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add sun9i A80 cpus (cpu special) clock supportChen-Yu Tsai2015-12-012-0/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | The "cpus" clock is the clock for the embedded processor in the A80. It is also part of the PRCM clock tree. This clock includes a pre- divider on one of its inputs. For now we are using a custom clock driver for it. In the future we may want to develop a generalized driver for these types of clocks, which also includes the AHB clock driver on sun[5678]i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add sun9i A80 apbs gates supportChen-Yu Tsai2015-12-011-0/+2
| | | | | | | | | | | | | | | | | | This patch adds support for the PRCM apbs clock gates found on the Allwinner A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 23:02:24 +0100