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path: root/drivers/clk/tegra/clk-tegra-periph.c (follow)
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* clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko2021-08-111-5/+1
* clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko2021-05-311-3/+3
* clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2020-12-101-1/+1
* clk: tegra: Mark fuse clock as criticalStephen Warren2020-01-081-1/+5
* clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2019-11-111-8/+0
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra: get rid of duplicate definesMarcel Ziswiler2018-12-141-3/+0
* clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver2018-07-251-11/+0
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-1/+1
* clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko2017-11-011-1/+1
* clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-011-0/+1
* clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-191-16/+0
* clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-191-4/+1
* clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid2017-08-241-1/+2
* clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-041-0/+6
* clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver2017-03-201-0/+21
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
* clk: tegra: Correct afi clock parentPeter De Schrijver2017-03-201-1/+1
* clk: tegra: Fix ISP clock modellingPeter De Schrijver2017-03-201-2/+9
* clk: tegra: Mark timer clock as criticalThierry Reding2016-06-221-1/+1
* clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2016-06-171-11/+12
* clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding2016-04-281-2/+0
* clk: tegra: Add dpaux1 clockThierry Reding2016-04-281-0/+1
* clk: tegra: Use correct parent for dpaux clockThierry Reding2016-04-281-1/+1
* clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding2016-04-281-1/+1
* clk: tegra: Constify peripheral clock registersThierry Reding2016-04-281-1/+1
* clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter2016-02-021-0/+1
* clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein2016-02-021-1/+1
* clk: tegra: Fix divider on VI_I2CRhyland Klein2016-01-251-1/+1
* clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein2015-11-201-4/+367
* clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0
* clk: tegra: Fix a bunch of sparse warningsThierry Reding2015-04-101-1/+1
* clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang2015-02-021-2/+0
* clk: tegra: SDMMC controllers are on APBAndrew Bresticker2015-02-021-8/+8
* clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver2014-06-251-2/+2
* clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-231-0/+6
* clk: tegra: Fix xusb_fs_src muxJim Lin2014-05-231-1/+3
* clk: tegra: Fix vic03 mux indexPeter De Schrijver2014-02-201-3/+1
* clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker2014-02-171-0/+4
* clk: tegra: Correct clock number for UARTEThierry Reding2014-02-171-1/+1
* clk: tegra124: Add new peripheral clocksPeter De Schrijver2013-11-261-0/+69
* clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-261-0/+6
* clk: tegra: add locking to periph clksPeter De Schrijver2013-11-261-15/+18
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-261-0/+596