| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: tegra: cclk_lp has a pllx/2 divider | Andrew Bresticker | 2014-02-17 | 1 | -1/+1 |
| * | clk: tegra: introduce common gen4 super clock | Peter De Schrijver | 2013-11-26 | 1 | -0/+149 |
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