linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: tegra: add fence_delay for clock registers	Peter De Schrijver	2018-03-08	1	-0/+7
*	clk: tegra: Add peripheral clock registration helper	Thierry Reding	2017-10-19	1	-0/+3
*	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	2017-08-24	1	-6/+0
*	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	2017-03-20	1	-1/+1
*	clk: tegra: Add super clock mux/divider	Peter De Schrijver	2017-03-20	1	-1/+6
*	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver	2017-03-20	1	-2/+2
*	clk: tegra: Fix type for m field	Peter De Schrijver	2017-03-20	1	-1/+1
*	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	2016-06-30	1	-0/+17
*	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	2016-04-28	1	-0/+6
*	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding	2016-04-28	1	-0/+17
*	clk: tegra: Constify peripheral clock registers	Thierry Reding	2016-04-28	1	-2/+2
*	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	2015-12-17	1	-0/+3
*	clk: tegra: Add Super Gen5 Logic	Bill Huang	2015-12-17	1	-0/+3
*	clk: tegra: pll: Add logic for SS	Bill Huang	2015-12-17	1	-0/+4
*	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein	2015-12-17	1	-0/+4
*	clk: tegra: pll: Add Set_default logic	Bill Huang	2015-12-17	1	-0/+11
*	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang	2015-12-17	1	-0/+4
*	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein	2015-12-17	1	-0/+9
*	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein	2015-12-17	1	-0/+24
*	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang	2015-11-20	1	-0/+4
*	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein	2015-11-20	1	-0/+13
*	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein	2015-11-20	1	-1/+14
*	clk: tegra: pll: Change misc_reg count from 3 to 6	Bill Huang	2015-11-20	1	-1/+3
*	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein	2015-11-20	1	-0/+1
*	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	2015-11-20	1	-1/+1
*	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein	2015-10-20	1	-1/+17
*	clk: tegra: Update struct tegra_clk_pll_params kerneldoc	Thierry Reding	2015-10-20	1	-3/+15
*	clk: tegra: Fix comments for structure definitions	Rhyland Klein	2015-10-20	1	-37/+37
*	clk: tegra: Introduce ability for SoC-specific reset control callbacks	Mikko Perttunen	2015-07-16	1	-0/+3
*	clk: tegra: EMC clock driver depends on EMC driver	Thierry Reding	2015-05-13	1	-0/+9
*	clk: tegra: Add EMC clock driver	Mikko Perttunen	2015-05-13	1	-0/+3
*	clk: tegra: Model oscillator as clock	Thierry Reding	2015-04-10	1	-4/+4
*	clk: tegra: Fix typo tabel -> table	Thierry Reding	2015-04-10	1	-1/+1
*	clk: tegra: Implement memory-controller clock	Thierry Reding	2014-11-26	1	-0/+2
*	clk: tegra: remove legacy reset APIs	Stephen Warren	2013-12-12	1	-1/+0
*	clk: tegra: implement a reset driver	Stephen Warren	2013-12-12	1	-1/+1
*	clk: tegra: add TEGRA_PERIPH_NO_GATE	Peter De Schrijver	2013-11-26	1	-0/+1
*	clk: tegra: add locking to periph clks	Peter De Schrijver	2013-11-26	1	-4/+6
*	clk: tegra: Add support for PLLSS	Peter De Schrijver	2013-11-26	1	-0/+5
*	clk: tegra: introduce common gen4 super clock	Peter De Schrijver	2013-11-26	1	-0/+3
*	clk: tegra: move PMC, fixed clocks to common files	Peter De Schrijver	2013-11-26	1	-0/+7
*	clk: tegra: move periph clocks to common file	Peter De Schrijver	2013-11-26	1	-2/+9
*	clk: tegra: move audio clk to common file	Peter De Schrijver	2013-11-26	1	-0/+4
*	clk: tegra: add clkdev registration infra	Peter De Schrijver	2013-11-26	1	-0/+7
*	clk: tegra: add common infra for DT clocks	Peter De Schrijver	2013-11-26	1	-0/+7
*	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver	2013-11-26	1	-23/+11
*	clk: tegra: Add TEGRA_PERIPH_NO_DIV flag	Peter De Schrijver	2013-11-26	1	-0/+1
*	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver	2013-11-26	1	-7/+9
*	clk: tegra: simplify periph clock data	Peter De Schrijver	2013-11-26	1	-8/+9
*	clk: tegra: T114: add DFLL DVCO reset control	Paul Walmsley	2013-06-18	1	-0/+2