summaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: tegra: probe deferral error reportingMarcel Ziswiler2018-10-171-2/+6
*-. Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd2018-08-158-40/+343
|\ \
| | * clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver2018-07-253-15/+12
| | * clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver2018-07-253-0/+278
| | * clk: tegra: Refactor fractional divider calculationPeter De Schrijver2018-07-254-25/+52
| | * clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo2018-07-251-0/+1
| |/
| |
| \
| \
| \
| \
| \
*-----. \ Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd2018-08-154-7/+15
|\ \ \ \ \ | |_|_|_|/ |/| | | |
| | | | * clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko2018-07-091-1/+1
| |_|_|/ |/| | |
| | | * clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko2018-07-091-2/+3
| |_|/ |/| |
| | * clk: tegra: Make vde a child of pll_c3Thierry Reding2018-07-091-1/+1
| | * clk: tegra: Make vic03 a child of pll_c3Thierry Reding2018-07-091-0/+1
| |/ |/|
| * clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen2018-07-091-3/+9
|/
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-131-3/+4
*-. Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Stephen Boyd2018-06-041-31/+11
|\ \
| | * clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman2018-06-021-31/+11
| |/
* | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-187-8/+39
* | clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko2018-05-181-4/+2
* | clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko2018-05-181-0/+14
|/
* clk: tegra: Fix pll_u rate configurationMarcel Ziswiler2018-03-121-0/+2
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-124-1/+4
* clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko2018-03-121-3/+3
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-128-36/+26
* clk: tegra: MBIST work around for Tegra210Peter De Schrijver2018-03-081-2/+342
* clk: tegra: add fence_delay for clock registersPeter De Schrijver2018-03-081-0/+7
* clk: tegra: Add la clock for Tegra210Peter De Schrijver2018-03-081-0/+14
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-11-1813-66/+102
|\
| * clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
| * clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen2017-11-013-13/+11
| * clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-11-011-1/+1
| * clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko2017-11-011-1/+1
| * clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko2017-11-011-5/+1
| * clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko2017-11-011-1/+1
| * clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-014-0/+4
| * clk: tegra: Mark APB clock as criticalJon Hunter2017-11-011-1/+1
| * clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal2017-10-191-8/+8
| * clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-192-16/+47
| * clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-194-13/+4
| * clk: tegra: Add peripheral clock registration helperThierry Reding2017-10-192-0/+11
| * clk: tegra: Check BPMP response return codeTimo Alho2017-10-191-5/+10
* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-022-0/+2
|/
* clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-241-2/+4
* clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-241-3/+3
* clk: tegra: Fix T210 PLLRE registrationAlex Frid2017-08-241-20/+1
* clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid2017-08-241-39/+9
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-244-49/+10
* clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-241-2/+4
* clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver2017-08-241-1/+1
* clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid2017-08-241-1/+2
* clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-241-4/+5
* clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver2017-08-241-0/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 08:23:14 +0100