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path: root/drivers/clk/zte (follow)
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* clk: zte: Mark pll config tables as constStephen Boyd2017-04-121-2/+2
* clk: zte: add pll_vga clock for zx296718Shawn Guo2017-04-121-0/+24
* clk: zte: pd_bit is not 0 on zx296718Shawn Guo2017-04-122-2/+16
* clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo2017-04-121-3/+3
* clk: zte: add i2s clocks for zx296718Baoyou Xie2017-02-101-0/+4
* clk: zte: add audio clocks for zx296718Jun Nie2017-01-103-0/+275
* clk: zx296718: do not panic on failureShawn Guo2017-01-101-9/+18
* clk: zx296718: register driver earlier with core_initcallShawn Guo2016-09-231-1/+5
* clk: zx: fix pointer case warningsArnd Bergmann2016-09-171-10/+10
* clk: zx296718: use builtin_platform_driver to simplify the codeWei Yongjun2016-09-171-5/+1
* clk: zx: register ZX296718 clocksJun Nie2016-09-143-0/+1050
* clk: zx: reform pll config info to ease code extensionJun Nie2016-09-142-9/+16
* clk: zte: Remove CLK_IS_ROOTStephen Boyd2016-04-161-2/+1
* clk: zx: Constify parent names in clock init dataJun Nie2015-07-281-20/+20
* clk: zx: Add audio and GPIO clock for zx296702Jun Nie2015-07-281-2/+90
* clk: zx: Add audio div clock method for zx296702Jun Nie2015-07-283-3/+149
* clk: zx: add clock support to zx296702Jun Nie2015-06-124-0/+863