| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag | Tejas Patel | 2020-01-23 | 1 | -5/+31 |
| * | clk: zynqmp: Fix divider calculation | Rajan Vaja | 2020-01-23 | 1 | -0/+46 |
| * | clk: zynqmp: Add support for get max divider | Rajan Vaja | 2020-01-23 | 1 | -0/+36 |
| * | clk: zynqmp: fix check for fractional clock | Michael Tretter | 2019-04-11 | 1 | -3/+6 |
| * | clk: zynqmp: do not export zynqmp_clk_register_* functions | Michael Tretter | 2019-04-11 | 1 | -1/+0 |
| * | drivers: clk: zynqmp: Allow zero divisor value | Rajan Vaja | 2019-04-11 | 1 | -0/+7 |
| * | drivers: clk: Add ZynqMP clock driver | Jolly Shah | 2018-10-09 | 1 | -0/+217 |
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