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path: root/drivers/clk/zynqmp/pll.c (follow)
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* clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rateQuanyang Wang2022-08-311-16/+15
* clk: zynqmp: replace warn_once with pr_debug for failed clock opsMichael Tretter2022-01-251-16/+16
* clk: zynqmp: Use firmware specific common clock flagsRajan Vaja2021-06-291-1/+3
* clk: zynqmp: pll: Remove some dead codeChristophe JAILLET2021-06-261-2/+0
* clk: zynqmp: fix compile testing without ZYNQMP_FIRMWAREMichal Simek2021-06-261-6/+16
* clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableQuanyang Wang2021-04-081-1/+11
* clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang2021-04-081-6/+6
* firmware: xilinx: Use APIs instead of IOCTLsRajan Vaja2020-04-281-10/+4
* firmware: xilinx: Remove eemi ops for clock_getdividerRajan Vaja2020-04-281-1/+1
* firmware: xilinx: Remove eemi ops for clock_setdividerRajan Vaja2020-04-281-2/+2
* firmware: xilinx: Remove eemi ops for clock_getstateRajan Vaja2020-04-281-2/+1
* firmware: xilinx: Remove eemi ops for clock_disableRajan Vaja2020-04-281-2/+1
* firmware: xilinx: Remove eemi ops for clock_enableRajan Vaja2020-04-281-2/+1
* clk: zynqmp: Warn user if clock user are more than allowedRajan Vaja2020-01-231-2/+4
* drivers: clk: Add ZynqMP clock driverJolly Shah2018-10-091-0/+335