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* dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong2019-04-011-1/+0
* dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet2019-04-011-0/+20
* clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong2019-03-191-1/+0
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-03-14143-1572/+8658
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| * clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPATTony Lindgren2019-03-081-1/+1
| * clk: fixup default index for of_clk_get_by_name()Kuninori Morimoto2019-03-081-1/+1
| * Merge branch 'clk-parent-rewrite' (early part) into clk-nextStephen Boyd2019-03-083-178/+230
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| | * clk: Move of_clk_*() APIs into clk.c from clkdev.cStephen Boyd2019-03-013-66/+62
| | * clk: Inform the core about consumer devicesStephen Boyd2019-03-013-9/+21
| | * clk: Introduce of_clk_get_hw_from_clkspec()Stephen Boyd2019-03-013-65/+69
| | * clk: core: clarify the check for runtime PMMiquel Raynal2019-03-011-6/+8
| | * clk: Combine __clk_get() and __clk_create_clk()Stephen Boyd2019-03-013-61/+98
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| *-----. \ Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-roc...Stephen Boyd2019-03-084-11/+15
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| | | | | * | clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclksFinley Xiao2019-01-071-2/+2
| | | | | * | clk: rockchip: fix frac settings of GPLL clock for rk3328Katsuhiro Suzuki2019-01-071-6/+6
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| | | | * | clk: mediatek: update clock driver of MT2712Weiyi Lu2019-02-051-2/+6
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| | * / / clk: samsung: fix typoMatteo Croce2019-01-241-1/+1
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| * | | Merge branch 'clk-at91' into clk-nextStephen Boyd2019-03-083-5/+10
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| | * | | clk: at91: programmable: remove unneeded register readNicolas Ferre2019-02-251-3/+0
| | * | | clk: at91: optimize clk_round_rate() for AUDIO_PLLMichał Mirosław2019-02-221-1/+8
| | * | | clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2Michał Mirosław2019-01-091-1/+2
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| *-------. \ \ Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk...Stephen Boyd2019-03-0811-50/+88
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| | | | | | * | | clk: mediatek: correct cpu clock name for MT8173 SoCSeiya Wang2019-02-261-2/+2
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| | | | | * | | clk: mediatek: Mark bus and DRAM related clocks as criticalJasper Mattsson2019-02-261-25/+43
| | | | | * | | clk: mediatek: Add flags to mtk_gateJasper Mattsson2019-02-264-3/+7
| | | | | * | | clk: mediatek: Add MUX_FLAGS macroJasper Mattsson2019-02-261-2/+6
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| | | | * / / clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocksBjorn Andersson2019-02-261-0/+5
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| | | * | | clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai2019-02-251-2/+2
| | | * | | clk: mediatek: add MUX_GATE_FLAGS_2chunhui dai2019-02-252-7/+15
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| | * | | clk: ingenic: Remove set but not used variable 'enable'YueHaibing2019-02-261-2/+1
| | * | | clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-02-221-1/+1
| | * | | clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-02-221-5/+5
| | * | | clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil2019-02-051-1/+1
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| *-----. \ \ Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd2019-03-0815-67/+155
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| | | | | * | | clk: mediatek: fix platform_no_drv_owner.cocci warningsYueHaibing2019-02-221-1/+0
| | | | | * | | clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing2019-02-221-9/+9
| | | | | * | | clk: qoriq: Improve an error messageDan Carpenter2019-02-221-2/+2
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| | | | * / / clk: x86: Move clk-lpss.h to platform_data/x86Andy Shevchenko2019-02-221-1/+1
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| | | * / / clk: fractional-divider: check parent rate only if flag is setKatsuhiro Suzuki2019-02-221-1/+1
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| | * | | clk: qcom: Make common clk_hw registrationsJeffrey Hugo2019-02-229-52/+29
| | * | | clk: qcom: smd: Add support for MSM8998 rpm clocksJeffrey Hugo2019-01-091-0/+63
| | * | | clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998Jeffrey Hugo2019-01-091-1/+1
| | * | | clk: qcom: Add missing freq for usb30_master_clk on 8998Jeffrey Hugo2019-01-091-0/+1
| | * | | clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocksJeffrey Hugo2019-01-091-0/+48
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| *-------. \ \ Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-q...Stephen Boyd2019-03-0811-39/+776
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| | | | | | * | | clk: actions: Add clock driver for S500 SoCManivannan Sadhasivam2019-02-223-0/+531
| | | | | | * | | clk: actions: Add configurable PLL delayManivannan Sadhasivam2019-02-222-7/+25
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| | | | | * | | clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clockTaniya Das2019-02-211-0/+1
| | | | | * | | clk: qcom: clk-rcg2: Introduce a cfg offset for RCGsTaniya Das2019-02-212-10/+16
| | | | | * | | clk: qcom: remove empty lines in clk-rcg.hVinod Koul2019-02-211-3/+0
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