| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | | | | | | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding | 2016-04-28 | 4 | -4/+48 | |
| | | * | | | | | | | | | clk: tegra: dfll: Make code more comprehensible | Thierry Reding | 2016-04-28 | 3 | -41/+37 | |
| | | * | | | | | | | | | clk: tegra: dfll: Reference CVB table instead of copying data | Thierry Reding | 2016-04-28 | 3 | -27/+17 | |
| | | * | | | | | | | | | clk: tegra: dfll: Update kerneldoc | Thierry Reding | 2016-04-28 | 1 | -5/+5 | |
| | | * | | | | | | | | | clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 | Lucas Stach | 2016-04-28 | 1 | -5/+6 | |
| | | * | | | | | | | | | clk: tegra: Initialize PLL_C to sane rate on Tegra30 | Lucas Stach | 2016-04-28 | 1 | -0/+1 | |
| | | * | | | | | | | | | clk: tegra: Fix pllre Tegra210 and add pll_re_out1 | Rhyland Klein | 2016-04-28 | 3 | -2/+66 | |
| | | * | | | | | | | | | clk: tegra: Add sor_safe clock | Thierry Reding | 2016-04-28 | 2 | -0/+5 | |
| | | * | | | | | | | | | clk: tegra: dpaux and dpaux1 are fixed factor clocks | Thierry Reding | 2016-04-28 | 3 | -2/+12 | |
| | | * | | | | | | | | | clk: tegra: Add dpaux1 clock | Thierry Reding | 2016-04-28 | 3 | -0/+3 | |
| | | * | | | | | | | | | clk: tegra: Use correct parent for dpaux clock | Thierry Reding | 2016-04-28 | 1 | -1/+1 | |
| | | * | | | | | | | | | clk: tegra: Add fixed factor peripheral clock type | Thierry Reding | 2016-04-28 | 3 | -0/+138 | |
| | | * | | | | | | | | | clk: tegra: Special-case mipi-cal parent on Tegra114 | Thierry Reding | 2016-04-28 | 2 | -2/+6 | |
| | | * | | | | | | | | | clk: tegra: Remove trailing blank line | Thierry Reding | 2016-04-28 | 1 | -1/+0 | |
| | | * | | | | | | | | | clk: tegra: Constify peripheral clock registers | Thierry Reding | 2016-04-28 | 5 | -7/+7 | |
| | * | | | | | | | | | | Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/g... | Stephen Boyd | 2016-05-03 | 2 | -169/+179 | |
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| | | * | | | | | | | | | clk: rockchip: fix the rk3399 cifout clock | Xing Zheng | 2016-04-25 | 1 | -5/+6 | |
| | | * | | | | | | | | | clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399 | Xing Zheng | 2016-04-25 | 1 | -157/+157 | |
| | | * | | | | | | | | | clk: rockchip: add some frequencies on the rk3399 PLL table | Xing Zheng | 2016-04-25 | 1 | -1/+10 | |
| | | * | | | | | | | | | clk: rockchip: assign more necessary rk3399 clock ids | Xing Zheng | 2016-04-25 | 1 | -6/+6 | |
| | | * | | | | | | | | | clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399 | Xing Zheng | 2016-04-25 | 1 | -2/+2 | |
| | | * | | | | | | | | | clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type | Colin Ian King | 2016-04-25 | 1 | -2/+2 | |
| | * | | | | | | | | | | Merge branch 'clk-hw-register' (early part) into clk-next | Stephen Boyd | 2016-04-21 | 10 | -87/+573 | |
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| | | * | | | | | | | | | | clk: fixed-rate: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -8/+36 | |
| | | * | | | | | | | | | | clk: gpio: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -11/+41 | |
| | | * | | | | | | | | | | clk: composite: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -12/+33 | |
| | | * | | | | | | | | | | clk: fractional-divider: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -5/+35 | |
| | | * | | | | | | | | | | clk: fixed-factor: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -7/+35 | |
| | | * | | | | | | | | | | clk: mux: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -6/+51 | |
| | | * | | | | | | | | | | clk: gate: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -7/+36 | |
| | | * | | | | | | | | | | clk: divider: Add hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -8/+83 | |
| | | * | | | | | | | | | | clkdev: Add clk_hw based registration APIs | Stephen Boyd | 2016-04-20 | 1 | -0/+64 | |
| | | * | | | | | | | | | | clk: Add clk_hw OF clk providers | Stephen Boyd | 2016-04-20 | 1 | -4/+81 | |
| | | * | | | | | | | | | | clk: Add {devm_}clk_hw_{register,unregister}() APIs | Stephen Boyd | 2016-04-20 | 1 | -0/+86 | |
| | | * | | | | | | | | | | clkdev: Remove clk_register_clkdevs() | Stephen Boyd | 2016-04-20 | 1 | -27/+0 | |
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| | * | | | | | | | | | | Merge branch 'clk-composite-unregister' into clk-next | Stephen Boyd | 2016-04-21 | 1 | -0/+15 | |
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| | | * | | | | | | | | | clk: composite: Add unregister function | Maxime Ripard | 2016-04-21 | 1 | -0/+15 | |
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| | * | | | | | | | | | clk: Add Oxford Semiconductor OXNAS Standard Clocks | Neil Armstrong | 2016-04-21 | 3 | -0/+202 | |
| | * | | | | | | | | | Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/k... | Stephen Boyd | 2016-04-20 | 4 | -18/+43 | |
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| | * | | | | | | | | | Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/g... | Stephen Boyd | 2016-04-20 | 4 | -81/+108 | |
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| | | * | | | | | | | | clk: rockchip: fix checkpatch warning in core code | Heiko Stuebner | 2016-04-20 | 3 | -22/+27 | |
| | | * | | | | | | | | clk: rockchip: drop unnecessary header comment | Heiko Stuebner | 2016-04-19 | 1 | -1/+0 | |
| | | * | | | | | | | | clk: rockchip: reign in some overly long lines in the rk3399 controller | Heiko Stuebner | 2016-04-19 | 1 | -58/+81 | |
| | * | | | | | | | | | clk: bcm2835: Fix PLL poweron | Eric Anholt | 2016-04-20 | 1 | -0/+4 | |
| | * | | | | | | | | | clk: bcm2835: Fix compiler warnings on 64-bit builds | Eric Anholt | 2016-04-20 | 1 | -4/+4 | |
| | * | | | | | | | | | clk: qoriq: add __init attribute | Julia Lawall | 2016-04-20 | 1 | -1/+2 | |
| | * | | | | | | | | | clk: ti: dra7-atl-clock: Fix of_node reference counting | Peter Ujfalusi | 2016-04-20 | 1 | -0/+2 | |
| | * | | | | | | | | | clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer' | Grygorii Strashko | 2016-04-16 | 2 | -0/+2 | |
| | * | | | | | | | | | clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec | Tero Kristo | 2016-04-16 | 1 | -0/+5 | |
| | * | | | | | | | | | clk: ti: dpll: add support for specifying max rate for DPLLs | Tero Kristo | 2016-04-16 | 1 | -0/+3 | |
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