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* Merge branch 'clk-of' into clk-nextStephen Boyd2018-12-144-8/+8
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| * clk: Use of_node_name_eq for node name comparisonsRob Herring2018-12-144-8/+8
* | Merge branch 'clk-vc5-suspend' into clk-nextStephen Boyd2018-12-141-0/+25
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| * | clk: vc5: Add suspend/resume supportMarek Vasut2018-12-141-0/+25
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* | Merge branch 'clk-fixes' into clk-nextStephen Boyd2018-12-147-6/+35
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| * | clk: qcom: qcs404: Fix gpll0_out_main parentSrinivas Kandagatla2018-12-101-1/+1
| * | clk: zynqmp: Off by one in zynqmp_is_valid_clock()Dan Carpenter2018-12-031-1/+1
| * | clk: mmp: Off by one in mmp_clk_add()Dan Carpenter2018-12-031-1/+1
| * | clk: mvebu: Off by one bugs in cp110_of_clk_get()Dan Carpenter2018-12-031-2/+2
| * | Merge branch 'clk-protected-binding' into clk-fixesStephen Boyd2018-11-281-0/+18
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| * | | clk: zynqmp: handle fixed factor param query errorRajan Vaja2018-11-141-0/+3
| * | | clk: qcom: gcc: Fix board clock node nameVinod Koul2018-11-091-1/+1
| * | | clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet2018-11-081-0/+13
| * | | clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt2018-11-081-0/+12
| * | | clk: fixed-factor: fix of_node_get-put imbalanceRicardo Ribalda Delgado2018-11-061-0/+1
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* | | Merge branch 'clk-qcom-8998-resets' into clk-nextStephen Boyd2018-12-141-64/+207
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| * | | clk: qcom: Drop unused 8998 clockJeffrey Hugo2018-12-141-14/+0
| * | | clk: qcom: Leave mmss noc on for 8998Jeffrey Hugo2018-12-141-0/+6
| * | | clk: qcom: Add missing msm8998 resetsJeffrey Hugo2018-12-111-0/+2
| * | | clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson2018-12-061-0/+75
| * | | clk: qcom: gcc-msm8998: Disable halt check of UFS clocksBjorn Andersson2018-12-061-3/+3
| * | | clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_atBjorn Andersson2018-12-061-28/+0
| * | | clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo2018-12-061-0/+87
| * | | clk: qcom: Add xo dummy clk on msm8998Stephen Boyd2018-12-061-0/+15
| * | | clk: qcom: Fix MSM8998 resetsJeffrey Hugo2018-12-031-19/+19
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*-------. \ \ Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp...Stephen Boyd2018-12-1427-27/+3361
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| | | | | * | | clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependantAbel Vesa2018-12-143-0/+8
| | | | | * | | clk: imx: remove redundant initialization of ret to zeroColin Ian King2018-12-101-1/+1
| | | | | * | | clk: imx: Add SCCG PLL typeLucas Stach2018-12-033-1/+267
| | | | | * | | clk: imx: Add fractional PLL output clockLucas Stach2018-12-033-0/+236
| | | | | * | | clk: imx: Add clock driver for i.MX8MQ CCMAbel Vesa2018-12-033-0/+626
| | | | | * | | clk: imx: Add imx composite clockAbel Vesa2018-12-033-0/+195
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| | | | * | | clk: imx: add imx8qxp lpcg driverAisheng Dong2018-12-143-1/+319
| | | | * | | clk: imx: add lpcg clock supportAisheng Dong2018-12-143-1/+121
| | | | * | | clk: imx: add imx8qxp clk driverAisheng Dong2018-12-143-0/+162
| | | | * | | clk: imx: add scu clock common partAisheng Dong2018-12-144-0/+292
| | | | * | | clk: imx: add configuration option for mmio clksAisheng Dong2018-12-144-2/+8
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| | | * | | clk: imx6q: add DCICx clocks gateAnson Huang2018-12-101-0/+2
| | | * | | clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang2018-12-101-0/+6
| | | * | | clk: imx7d: remove UART1 clock settingAnson Huang2018-11-061-3/+0
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| | * | | clk: imx6q: handle ENET PLL bypassLucas Stach2018-12-101-6/+57
| | * | | clk: imx6q: optionally get CCM inputs via standard clock handlesLucas Stach2018-12-101-5/+17
| | * | | clk: imx6q: reset exclusive gates on initLucas Stach2018-12-101-1/+5
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| * | | clk: imx: add imx7ulp clk driverA.s. Dong2018-12-032-0/+221
| * | | clk: imx: implement new clk_hw based APIsA.s. Dong2018-12-032-0/+84
| * | | clk: imx: make mux parent strings constA.s. Dong2018-12-033-9/+13
| * | | clk: imx: add imx7ulp composite clk supportA.s. Dong2018-12-033-0/+94
| * | | clk: imx: add pfdv2 supportA.s. Dong2018-12-033-1/+208
| * | | clk: imx: add pllv4 supportA.s. Dong2018-12-033-0/+188
| * | | clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag supportA.s. Dong2018-12-031-0/+10
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