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* Merge tag 'armsoc-multiplatform' of ↵Linus Torvalds2015-04-222-0/+144
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform code changes from Olof Johansson: "The changes here belong to two main platforms: - Atmel At91 is flipping the bit and going multiplatform. This includes some cleanups and removal of code, and the final flip of config dependencies - Shmobile has several platforms that are going multiplatform, but this branch also contains a bunch of cleanups that they weren't able to keep separate in a good way. THere's also a removal of one of their SoCs and the corresponding boards (sh7372 and mackerel)" * tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (67 commits) ARM: at91/pm: move AT91_MEMCTRL_* to pm.h ARM: at91/pm: move the standby functions to pm.c ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected ARM: at91: add a Kconfig dependency on multi-platform ARM: at91: drop AT91_TIMER_HZ ARM: at91: remove hardware.h ARM: at91: remove SoC headers ARM: at91: remove useless mach/cpu.h ARM: at91: remove unused headers ARM: at91: switch at91_dt_defconfig to multiplatform ARM: at91: switch to multiplatform ARM: shmobile: r8a7778: enable multiplatform target ARM: shmobile: bockw: add sound to DT ARM: shmobile: r8a7778: add sound to DT ARM: shmobile: bockw: add devices hooked up to i2c0 to DT DT: i2c: add trivial binding for OKI ML86V7667 video decoder ARM: shmobile: r8a7778: common clock framework CPG driver ARM: shmobile: bockw dts: set extal clock frequency ARM: shmobile: bockw dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4: Remove legacy code ...
| * ARM: shmobile: r8a7778: common clock framework CPG driverUlrich Hecht2015-02-272-0/+144
| | | | | | | | | | | | | | | | | | Driver for the r8a7778's clocks that depend on the mode bits. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | Merge tag 'clk-for-linus-4.1' of ↵Linus Torvalds2015-04-2189-833/+10735
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clock framework updates from Michael Turquette: "The changes to the common clock framework for 4.0 are mostly new clock drivers and updates to existing ones for feature enhancements and bug fixes. There is more churn than usual in the framework core due to the change to introduce per-user unique struct clk pointers in 4.0. This caused several regressions to surface, some of which were sent as fixes to 4.0. New generic clock drivers were added for GPIO- and PWM-based clock controllers. Additionally the common clk-divider code recieved several fixes to the way it rounds rates" * tag 'clk-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (91 commits) clk: check ->determine/round_rate() return value in clk_calc_new_rates clk: at91: usb: propagate rate modification to the parent clk clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC clk: don't use __initconst for non-const arrays clk: at91: change to using endian agnositc IO clk: clk-gpio-gate: Fix active low clk: Add PWM clock driver clk: Add clock driver for mb86s7x clk: pxa: pxa3xx: add missing os timer clock clk: tegra: Use the proper parent for plld_dsi clk: tegra: Use generic tegra_osc_clk_init() on Tegra114 clk: tegra: Model oscillator as clock clk: tegra: Add peripheral registers for bank Y clk: tegra: Register the proper number of resets clk: tegra: Remove needless initializations clk: tegra: Use consistent indentation clk: tegra: Various whitespace cleanups clk: tegra: Enable HDA to HDMI clocks on Tegra124 clk: tegra: Fix a bunch of sparse warnings clk: tegra: Fix typo tabel -> table ...
| * | clk: check ->determine/round_rate() return value in clk_calc_new_ratesBoris Brezillon2015-04-131-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ->determine_rate() and ->round_rate() can return the closest rate to the requested one or an error code. clk_calc_new_rates is assuming these functions can't return a negative value, which leads to a undefined behavior when the clk implementation returns such an error code. Fix this by returning NULL in case ->determine_rate() or ->round_rate() returned an error code. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: at91: usb: propagate rate modification to the parent clkBoris Brezillon2015-04-131-15/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The at91sam9n12 and at91sam9x5 usb clocks do not propagate rate modification requests to their parents. This causes a bug when the PLLB is left uninitialized by the bootloader (PLL multiplier set to 0, or in other words, PLL rate = 0 Hz). Implement the determinate_rate method and propagate the change rate request to the parent clk. Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Bo Shen <voice.shen@atmel.com> Tested-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoCBartlomiej Zolnierkiewicz2015-04-131-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") enabled ARMCLK down feature on all Exynos4 SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature causes a lockup when ondemand cpufreq governor is used. Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs. This patch was tested on: - Exynos4210 SoC based Trats board - Exynos4210 SoC based Origen board - Exynos4412 SoC based Trats2 board - Exynos4412 SoC based Odroid-U3 board Cc: Daniel Drake <drake@endlessm.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: don't use __initconst for non-const arraysUwe Kleine-König2015-04-1312-100/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | Merge tag 'clk/for-4.1' of ↵Michael Turquette2015-04-118-71/+69
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk/tegra: Changes for v4.1-rc1 These are mostly cleanups that I've been carrying in my local tree for far too long. In addition to those, there are some preparatory patches for the upcoming Tegra210 support and a patch to enable clocks needed for HDMI audio support.
| | * | clk: tegra: Use the proper parent for plld_dsiThierry Reding2015-04-101-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding2015-04-101-31/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason why Tegra114 cannot use the same generic code to set up the oscillator, clk_m and pll_ref clocks. The only effective change that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but since these clocks are all fixed it is not needed anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Model oscillator as clockThierry Reding2015-04-104-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Add peripheral registers for bank YThierry Reding2015-04-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Register the proper number of resetsThierry Reding2015-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of resets controls is 32 times the number of peripheral register banks rather than 32 times the number of clocks. This reduces (drastically) the number of reset controls registered from 10080 (315 clocks * 32) to 224 (6 peripheral register banks * 32). This also fixes a potential crash because trying to use any of the excess reset controls (224-10079) would have caused accesses beyond the array bounds of the peripheral register banks definition array. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver") Cc: stable@vger.kernel.org # 3.14+ Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Remove needless initializationsThierry Reding2015-04-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ret variable is often explicitly initialized to 0, but there is no need to do so in many cases because it will immediately be overwritten with the return value from a function. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Use consistent indentationThierry Reding2015-04-101-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the .dev_id entries in the devclks table were oddly indented. Make them consistent with the rest of the table. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Various whitespace cleanupsThierry Reding2015-04-102-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Make usage of blank lines as separators more consistent. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid2015-04-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the clocks used for HDMI audio played through the HDA controller. Initialize the codec clock to 48Mhz and the HDA clock to 102MHz per the TRM. Signed-off-by: Dylan Reid <dgreid@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Fix a bunch of sparse warningsThierry Reding2015-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The second to last parameter of the TEGRA_CLK_PERIPH macro denotes a table and should therefore users should pass in NULL instead of 0. Fixes a bunch of sparse warnings like this: warning: Using plain integer as NULL pointer Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | clk: tegra: Fix typo tabel -> tableThierry Reding2015-04-101-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | The clock initialization structure is named struct clk_init_table. Update the kerneldoc comment to use the correct name. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: clk-gpio-gate: Fix active lowMartin Fuzzey2015-04-111-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The active low flag in the DT cell is currently ignored. This occurs because of_get_named_gpio_flags() does not apply the flags to the underlying struct gpio_desc so the test in clk_register_gpio_gate() was bogus. Note that this patch changes the internal kernel API for clk_register_gpio_gate() but there are currently no other users. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: Add PWM clock driverPhilipp Zabel2015-04-103-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some board designers, when running out of clock output pads, decide to (mis)use PWM output pads to provide a clock to external components. This driver supports this practice by providing an adapter between the PWM and clock bindings in the device tree. As the PWM bindings specify the period in the device tree, this is a fixed clock. Tested-by: Janusz Uzycki <j.uzycki@elproma.com.pl> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: Add clock driver for mb86s7xJassi Brar2015-04-102-0/+387
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CRG11 clock controller is managed by remote f/w. This driver simply maps Linux CLK ops onto mailbox api. Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Vincent Yang <vincent.yang@socionext.com> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: pxa: pxa3xx: add missing os timer clockRobert Jarzmik2015-04-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pxa3xx scheduler relies on the pxa-timer, which requires a clock for its rate. As the clock handling will be taken over by the clock framework, add this missing clock. The miss was discovered by attempting to run a zylonite platform in a device-tree configuration, with the future patch to shift clocks handling to clock framework applied. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: versatile: test returned valueJulia Lawall2015-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put NULL test on the result of the previous call instead on one of its arguments. A simplified version of the semantic match that finds this problem is as follows (http://coccinelle.lip6.fr/): // <smpl> r@ expression *e1; expression *e2; identifier f; statement S1,S2; @@ e1 = f(...,e2,...); ( if (e1 == NULL || ...) S1 else S2 | *if (e2 == NULL || ...) S1 else S2 ) // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: Fix parent_map translationsGeorgi Djakov2015-04-082-11/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we introduced the parent_map tables, we missed to update some of the functions where mapping is translated. Fix this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: fix driver dependenciesBartlomiej Zolnierkiewicz2015-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for Qualcomm's clock controllers should be available only on Qualcomm platforms. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: Add EBI2 clocks for IPQ806xArchit Taneja2015-04-061-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: constify of_device_id arrayFabian Frederick2015-04-017-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_id is always used as const. (See driver.of_match_table and open firmware functions) __initdata updated to __initconst for static const struct of_device_id ti_clkdm_match_table[] Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: samsung: exynos3250: Add driver for CMU_ISP clock domainTomasz Figa2015-03-311-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock controller for CMU ISP clock domain on Exynos3250, providing clocks for FIMC-IS subsystem. [b.michalska: use samsung_cmu_register_one to register the provider; updated DT binding documentation] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Beata Michalska <b.michalska@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> [s.nawrocki: added __init attribute which was missing in function exynos3250_cmu_platform_init() in function, which has been] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: samsung: Add CLKOUT driver support for Exynos3250 SoCInha Song2015-03-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add CLKOUT driver support for Exynos3250 SoC. Exynos3250 SoC PMU_DEBUG is the same with Exynos4's PMU_DEBUG including CLKOUT mux. So we can use the exynos4's clkout init function for Exynos3250 without the need to add new function. Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: cdce706: Constify struct regmap_configKrzysztof Kozlowski2015-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: si570: Constify struct regmap_configKrzysztof Kozlowski2015-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: si5351: Constify clock names and struct regmap_configKrzysztof Kozlowski2015-03-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Replace doubled const in the arrays of clock names with proper const pointer to const data. This fixes the warnings: drivers/clk/clk-si5351.c:71:25: warning: duplicate const drivers/clk/clk-si5351.c:74:25: warning: duplicate const drivers/clk/clk-si5351.c:77:25: warning: duplicate const drivers/clk/clk-si5351.c:80:25: warning: duplicate const Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: fix simple_return.cocci warningsFengguang Wu2015-03-271-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/qcom/clk-pll.c:74:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: Fix ipq806x LCC frequency tablesStephen Boyd2015-03-271-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These frequency tables list the wrong rates. Either they don't have the correct frequency at all, or they're specified in kHz instead of Hz. Fix it. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | Merge tag 'sunxi-clocks-for-4.1' of ↵Michael Turquette2015-03-253-103/+316
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.1 The usual round of clock changes for the Allwinner SoCs. There is nothing really standing out here, but a few changes and fixes, most notably to allow the AHB clock to be parented to a PLL, instead of the CPU clock to avoid any AHB rate change due to cpufreq.
| | * | clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6Chen-Yu Tsai2015-03-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Make divs clocks specify which output is the base factor clockChen-Yu Tsai2015-03-251-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current sunxi clock driver has the base factor clock of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown. This patch makes the divs clocks data structure specify which output is the factor clock, and updates all current divs clocks accordingly. We can then add new outputs after the factor clocks, at least not breaking backward compatibility with regards to the devicetree bindings. Also replace kzalloc with kcalloc in sunxi_divs_clk_setup(). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Register divs clocks before factor clocksChen-Yu Tsai2015-03-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to reparent AHB clock to PLL6 on sun5i/sun7i using the assigned clocks properties. AHB is a factor clock, while PLL6 is a divs clock. Register divs clocks before factor clocks so reparenting works. This is only needed because we do the reparenting on the clock provider. The proper way to fix this is to split out all the old sunxi clocks into separate CLK_OF_DECLARE statements, like we are doing for sun9i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Add "cpu" to list of protected clocks for sun5iChen-Yu Tsai2015-03-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the ahb clock on sun5i/sun7i is muxable, ahb is no longer guaranteed to be a child of the cpu clock. Add the cpu clock to the list of protected clocks so it doesn't get disabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai2015-03-211-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AHB clock on sun5i and sun7i are muxable divider clocks. Use a factors clock to support them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Add support for sun9i A80 USB clocks and resetsChen-Yu Tsai2015-02-231-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller/phy clocks and reset controls are in a separate address block, unlike previous SoCs where they were in the clock controller. Also, access to the address block is controlled by a clock gate to AHB. Add support for resets requiring a clock to be enabled when asserting/deasserting the reset controls, and add the sun9i USB clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi: Move USB clocks to separate fileChen-Yu Tsai2015-02-233-88/+191
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB clocks originally shared code with the gates clocks, but had additional reset controllers. Move these to a separate file. This will allow us to add new support for slightly different USB clocks, such as on the A80, without affecting gates clocks, and also facilitate the migration of gates clocks to a generic solution. This also cleans up the USB clocks code slightly, such as adding newlines, getting rid of the unused clkdev call, using a simple u32 instead of BITMAP for the clock masks, using BIT() macro to declare the clock bitmasks, and using of_io_request_and_map() to get the I/O address. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | Merge branch 'for-4.1-clk-ti' of github.com:t-kristo/linux-pm into clk-nextMichael Turquette2015-03-2514-72/+318
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| | * | clk: ti: Implement FAPLL set_rate for the PLLTony Lindgren2015-03-241-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a fractional divider for the synthesizer, just implement a simple multiply logic for the PLL. It seems the PLL divider needs to have also the multiplier set for the PLL to lock. At least I have not yet figured out if divided rates are doable. So let's just ignore the PLL divider for now as the synthesizer has both integer and fractional dividers so we don't even need to use the PLL divider for the rates we know work with PLL locking. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | clk: ti: Implement FAPLL set_rate for the synthesizerTony Lindgren2015-03-241-2/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can pretty much get any rate out of the FAPLL because of the fractional divider. Let's first try just adjusting the post divider, and if that is not enough, then reprogram both the fractional divider and the post divider. Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | clk: ti: Fix FAPLL recalc_rate for rounding errorsTony Lindgren2015-03-241-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to round the calculated value to have it match the requested rate. While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we will need it in later patches for set_rate. And let's remove two unused includes. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | clk: ti: DRA7: Add timer_sys_ck aliases for Timers 13 through 16Suman Anna2015-03-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name timer_sys_ck for setting a timer's clock source for the source index OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for the Timers 13 through 16 for this clock name, so add the same. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | clk: ti: DRA7: Correct timer_sys_ck clock aliases for TimersSuman Anna2015-03-241-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent of a timer node using 3 different values that use fixed parent names for the clocks. The parent name, timer_sys_ck, is used for setting the parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock input. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * | clk: ti: OMAP5: Correct the DT clock aliases for timersSuman Anna2015-03-241-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT clock aliases for Timers use the legacy (non-DT) device names and a source clock named sys_ck. OMAP5 is DT-boot only, so correct the DT clock aliases to use the DT device names instead. Also, the source clock name is corrected from 'sys_ck' to 'timer_sys_ck', the name used by the OMAP dmtimer driver. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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