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* clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepllMatthew McClintock2016-03-301-0/+10
| | | | | | | | Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq4019: switch remaining defines to enumsMatthew McClintock2016-03-301-35/+25
| | | | | | | | | When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Make reset_control_ops constPhilipp Zabel2016-03-302-2/+2
| | | | | | | The qcom_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
| | | | | | | The rst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sunxi: Make reset_control_ops constPhilipp Zabel2016-03-303-3/+3
| | | | | | | | The sunxi_ve_reset_ops, sun9i_mmc_reset_ops, and sunxi_usb_reset_ops structures are never modified. Make them const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: atlas7: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
| | | | | | | The atlas7_rst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: rockchip: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
| | | | | | | | The rockchip_softrst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mmp: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
| | | | | | | The mmp_clk_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mediatek: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
| | | | | | | | The mtk_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2016-03-23163-2357/+5232
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The clk changes for this release cycle are mostly dominated by new device support in terms of LoC, but there has been some cleanup in the core as well as the usual minor clk additions to various drivers. Core: - parent tracking has been simplified - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started - of_clk_init() doesn't consider disabled DT nodes anymore - clk_unregister() had an error path bug squashed - of_clk_get_parent_count() has been fixed to only return unsigned ints - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone New Drivers: - NXP LPC18xx creg - QCOM IPQ4019 GCC - TI dm814x ADPLL - i.MX6QP Updates: - Cyngus audio clks found on Broadcom iProc devices - Non-critical fixes for BCM2385 PLLs - Samsung exynos5433 updates for clk id errors, HDMI support, suspend/resume simplifications - USB, CAN, LVDS, and FCP clks on shmobile devices - sunxi got support for more clks on new SoCs and went through a minor refactoring/rewrite to use a simpler factor clk construct - rockchip added some more clk ids and added suport for fraction dividers - QCOM GDSCs in msm8996 - A new devm helper to make adding custom actions simpler (acked by Greg)" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits) clk: bcm2835: fix check of error code returned by devm_ioremap_resource() clk: renesas: div6: use RENESAS for #define clk: renesas: Rename header file renesas.h clk: max77{686,802}: Remove CLK_IS_ROOT clk: versatile: Remove CLK_IS_ROOT clk: sunxi: Remove use of variable length array clk: fixed-rate: Remove CLK_IS_ROOT clk: qcom: Remove CLK_IS_ROOT doc: dt: add documentation for lpc1850-creg-clk driver clk: add lpc18xx creg clk driver clk: lpc32xx: fix compilation warning clk: xgene: Add missing parenthesis when clearing divider value clk: mb86s7x: Remove CLK_IS_ROOT clk: x86: Remove clkdev.h and clk.h includes clk: x86: Remove CLK_IS_ROOT clk: mvebu: Remove CLK_IS_ROOT clk: renesas: move drivers to renesas directory clk: si5{14,351,70}: Remove CLK_IS_ROOT clk: scpi: Remove CLK_IS_ROOT clk: s2mps11: Remove CLK_IS_ROOT ...
| * clk: bcm2835: fix check of error code returned by devm_ioremap_resource()Vladimir Zapolskiy2016-03-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The change fixes potential oops while accessing iomem on invalid address, if devm_ioremap_resource() fails due to some reason. The devm_ioremap_resource() function returns ERR_PTR() and never returns NULL, which makes useless a following check for NULL. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Fixes: 5e63dcc74b30 ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates") Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: div6: use RENESAS for #defineSimon Horman2016-03-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Name the #define guarding compilation of this header __RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__. This is a follow-up to renaming the directory in which this file lives from shmobile to renesas which is in turn part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: Rename header file renesas.hSimon Horman2016-03-168-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename files. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: max77{686,802}: Remove CLK_IS_ROOTStephen Boyd2016-03-152-5/+0
| | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: versatile: Remove CLK_IS_ROOTStephen Boyd2016-03-154-9/+6
| | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: sunxi: Remove use of variable length arrayStephen Boyd2016-03-151-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Using an array allocated on the stack may lead to stack overflows and other problems so let's move the allocation to the heap instead. This silences the following checker warning as well. drivers/clk/sunxi/clk-sun8i-mbus.c:36:29: warning: Variable length array is used Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: fixed-rate: Remove CLK_IS_ROOTStephen Boyd2016-03-041-2/+1
| | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Remove CLK_IS_ROOTStephen Boyd2016-03-047-152/+2
| | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: add lpc18xx creg clk driverJoachim Eastwood2016-03-042-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | The CREG block on lpc18xx contains configuration register for two low power clocks. Support enabling of these two clocks with a clk driver that access CREG trough the syscon regmap interface. These clocks are needed to support peripherals like the internal RTC on lpc18xx. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * Merge tag 'v4.6-rockchip-clk2' of ↵Stephen Boyd2016-03-046-61/+83
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull second batch of rockchip clk updates from Heiko Stuebner: Inclusion of the rk3368 fractional dividers into our handling scheme, fixes for missing error-handling in mmc-phase, inverters and cpu-clocks and some more clock-ids. * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: include downstream muxes into fractional dividers on rk3368 clk: rockchip: set the clock ids for RK3228 HDMI clk: rockchip: set the clock ids for RK3228 VOP clk: rockchip: add the tsadc clocks found on rk3228 SoCs clk: rockchip: add the new clock ids for RK3228 HDMI clk: rockchip: add the new clock ids for RK3228 VOP clk: rockchip: add id of the tsadc clock found on rk3228 SoCs clk: rockchip: fix coding style for clk-cpu.c clk: rockchip: don't return NULL when registering mmc branch fails clk: rockchip: don't return NULL when registering inverter fails clk: rockchip: check grf when waiting pll lock clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
| | * clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang2016-02-261-37/+60
| | | | | | | | | | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: set the clock ids for RK3228 HDMIYakir Yang2016-02-261-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: set the clock ids for RK3228 VOPYakir Yang2016-02-261-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: add the tsadc clocks found on rk3228 SoCsCaesar Wang2016-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the needed clocks for rk3228 tsadc. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: fix coding style for clk-cpu.cShawn Lin2016-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: don't return NULL when registering mmc branch failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_mmc fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: don't return NULL when registering inverter failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_inverter fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: check grf when waiting pll lockShawn Lin2016-02-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | rockchip_clk_get_grf pass on return value from syscon_regmap_lookup_by_phandle, so we check grf to make sure whether to do the following things or not. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: disable alt_parent clk in err cases when registering cpuclkShawn Lin2016-02-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add clk_disable_unprepare to handle cpuclk->alt_parent if rockchip_clk_register_cpuclk fails. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: lpc32xx: fix compilation warningSylvain Lemieux2016-03-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the following false positives compilation warning: - drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register': warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized] - drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate': warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized] warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized] warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized] Tested using gcc version 4.7.3. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> [sboyd@codeaurora.org: Drop assignment of hw to NULL as return silences it and is less likely to lead to hiding problems later] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: xgene: Add missing parenthesis when clearing divider valueLoc Ho2016-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the initial fix for non-zero divider shift value, the parenthesis was missing after the negate operation. This patch adds the required parenthesis. Otherwise, lower bits may be cleared unintentionally. Signed-off-by: Loc Ho <lho@apm.com> Acked-by: Toan Le <toanle@apm.com> Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: mb86s7x: Remove CLK_IS_ROOTStephen Boyd2016-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: x86: Remove clkdev.h and clk.h includesStephen Boyd2016-03-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is a clk provider and not a clk consumer, so remove the clk.h include. Also, drop clkdev.h because there's not clkdev usage here either. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: x86: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: mvebu: Remove CLK_IS_ROOTStephen Boyd2016-03-032-8/+6
| | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: renesas: move drivers to renesas directorySimon Horman2016-03-0316-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | Merge branch 'clk-shmobile-for-v4.6' of ↵Stephen Boyd2016-03-032-2/+21
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull shmobile clk updates from Geert Uytterhoeven: - Fix a bug in the div6 clock driver that was exposed by CAN support on R-Car H3, - Add more module clocks for R-Car H3. * 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: shmobile: r8a7795: Add CAN FD peripheral clock clk: shmobile: r8a7795: Add CANFD clock clk: shmobile: r8a7795: Add CAN peripheral clock clk: shmobile: div6: Fix .recalc_rate() using a stale divisor clk: shmobile: r8a7795: Add LVDS module clock clk: shmobile: r8a7795: Add FCP clocks
| | * | clk: shmobile: r8a7795: Add CAN FD peripheral clockRamesh Shanmugasundaram2016-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: r8a7795: Add CANFD clockRamesh Shanmugasundaram2016-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: r8a7795: Add CAN peripheral clockRamesh Shanmugasundaram2016-02-261-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: div6: Fix .recalc_rate() using a stale divisorGeert Uytterhoeven2016-02-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpg_div6_clock_set_rate() only programs the new divisor if the clock isn't stopped. If the clock is stopped, it will update the cached divisor value only, which will be programmed into the clock registers when enabling the clock later. However, cpg_div6_clock_recalc_rate() reads the divisor from the clock registers instead of using the cached value, leading to an incorrect result if the clock is currently stopped. Make cpg_div6_clock_recalc_rate() use the cached value to fix this. Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
| | * | clk: shmobile: r8a7795: Add LVDS module clockLaurent Pinchart2016-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The parent clock hasn't been validated yet. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: r8a7795: Add FCP clocksLaurent Pinchart2016-02-261-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parent clock isn't documented in the datasheet, use S2D1 as a best guess for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: si5{14,351,70}: Remove CLK_IS_ROOTStephen Boyd2016-03-033-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: scpi: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: s2mps11: Remove CLK_IS_ROOTStephen Boyd2016-03-031-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Andi Shyti <andi.shyti@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: pwm: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: efm32gg: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: zynq: Remove CLK_IS_ROOTStephen Boyd2016-03-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: ux500: Remove CLK_IS_ROOTStephen Boyd2016-03-033-84/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 08:45:25 +0100