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| | | | | * | | | clk: imx: Add imx composite clockAbel Vesa2018-12-033-0/+195
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| | | | * | | | clk: imx: add imx8qxp lpcg driverAisheng Dong2018-12-143-1/+319
| | | | * | | | clk: imx: add lpcg clock supportAisheng Dong2018-12-143-1/+121
| | | | * | | | clk: imx: add imx8qxp clk driverAisheng Dong2018-12-143-0/+162
| | | | * | | | clk: imx: add scu clock common partAisheng Dong2018-12-144-0/+292
| | | | * | | | clk: imx: add configuration option for mmio clksAisheng Dong2018-12-144-2/+8
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| | | * | | | clk: imx6q: add DCICx clocks gateAnson Huang2018-12-101-0/+2
| | | * | | | clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang2018-12-101-0/+6
| | | * | | | clk: imx7d: remove UART1 clock settingAnson Huang2018-11-061-3/+0
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| | * | | | clk: imx6q: handle ENET PLL bypassLucas Stach2018-12-101-6/+57
| | * | | | clk: imx6q: optionally get CCM inputs via standard clock handlesLucas Stach2018-12-101-5/+17
| | * | | | clk: imx6q: reset exclusive gates on initLucas Stach2018-12-101-1/+5
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| * | | | clk: imx: add imx7ulp clk driverA.s. Dong2018-12-032-0/+221
| * | | | clk: imx: implement new clk_hw based APIsA.s. Dong2018-12-032-0/+84
| * | | | clk: imx: make mux parent strings constA.s. Dong2018-12-033-9/+13
| * | | | clk: imx: add imx7ulp composite clk supportA.s. Dong2018-12-033-0/+94
| * | | | clk: imx: add pfdv2 supportA.s. Dong2018-12-033-1/+208
| * | | | clk: imx: add pllv4 supportA.s. Dong2018-12-033-0/+188
| * | | | clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag supportA.s. Dong2018-12-031-0/+10
| * | | | clk: imx: add gatable clock divider supportA.s. Dong2018-12-033-0/+226
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*-------. \ \ \ Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd2018-12-1446-230/+3116
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| | | | | * | | | clk: rockchip: add clock-id to gate of ACODEC for rk3328Katsuhiro Suzuki2018-11-261-1/+1
| | | | | * | | | clk: rockchip: fix I2S1 clock gate register for rk3328Katsuhiro Suzuki2018-11-191-1/+1
| | | | | * | | | clk: rockchip: make rk3188 hclk_vio_bus criticalMark Yao2018-11-151-1/+2
| | | | | * | | | clk: rockchip: fix rk3188 sclk_mac_lbtest parameter orderingHeiko Stuebner2018-11-151-2/+2
| | | | | * | | | clk: rockchip: fix rk3188 sclk_smc gate dataFinley Xiao2018-11-151-2/+2
| | | | | * | | | clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker2018-11-121-1/+1
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| | | | * | | | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd2018-12-137-71/+870
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| | | | | * | | | clk: meson: axg-audio: use the clk input helper functionJerome Brunet2018-12-111-59/+24
| | | | | * | | | clk: meson: add clk-input helper functionJerome Brunet2018-12-053-0/+50
| | | | | * | | | clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-032-10/+782
| | | | | * | | | clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-032-0/+6
| | | | | * | | | clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
| | | | | * | | | clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong2018-11-271-1/+7
| | | | * | | | | clk: meson: Mark some things staticStephen Boyd2018-12-032-6/+6
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| | | | * | | | clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-232-1/+256
| | | | * | | | clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-232-12/+12
| | | | * | | | clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2018-11-232-0/+6
| | | | * | | | clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
| | | | * | | | clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
| | | | * | | | clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
| | | | * | | | clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
| | | | * | | | clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
| | | | * | | | clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl2018-11-231-0/+19
| | | | * | | | clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
| | | | * | | | clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
| | | | * | | | clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
| | | | * | | | clk: meson-gxbb: Add video clocksNeil Armstrong2018-11-231-0/+722
| | | | * | | | dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong2018-11-231-2/+24
| | | | * | | | clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong2018-11-231-2/+49
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