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* clk: qcom: ipq8074: add misc resets for PCIE and NSSAbhishek Sahu2017-12-221-0/+42
| | | | | | | | | PCIE and NSS has MISC reset register in which single register has multiple reset bit. The patch adds these resets with its corresponding reset bits. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: add GP and Crypto clocksAbhishek Sahu2017-12-221-0/+199
| | | | | | | | | | | - It has 3 general purpose clock controller which supplies the clock in GPIO pins. - It has Crypto Engine which has AXI, AHB and Core clocks. Other non APSS processors can also use Crypto Engine so these clocks are marked as VOTED clocks. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: add NSS ethernet port clocksAbhishek Sahu2017-12-221-0/+1288
| | | | | | | | | | | | IPQ8074 has 6 ethernet ports which supports all ethernet speeds from 10Mpbs to 10 Gpbs and each speed requires different clock rates. Each port has separate TX and RX clocks. These clocks use separate external UNIPHY PLL’s which will be registered with separate NSS driver. The clock frequency is 125 Mhz for UNIPHY0 and 312.5 Mhz for UNIPHY1 and UNIPHY2. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: add NSS clocksAbhishek Sahu2017-12-221-0/+1034
| | | | | | | | | | | IPQ8074 has NSS (Network Switching System) which has 2 UBI cores and hardware crypto engine. Some clocks are separate for each UBI core and remaining NSS clocks are common. The BIAS_PLL (300 Mhz) and BIAS_PLL_NSS_NOC (416.5 Mhz) are external fixed clocks and will be registered from dtsi or NSS driver. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: add PCIE, USB and SDCC clocksAbhishek Sahu2017-12-221-0/+994
| | | | | | | | | | | | | | | | | - It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC AXI and PIPE clocks. - It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE, SYS NOC, mock UTMI and master clocks. - It has 2 instances of SDCC which uses APSS and AHB clock. SDCC1 requires ICE core clock also. - All the PIPE clocks are external clocks which will be registered in clock framework by PHY drivers. The enabling and disabling of PIPE RCG clocks are dependent upon PHY initialization sequence so BRANCH_HALT_DELAY flag is required for these clocks. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: add remaining PLL’sAbhishek Sahu2017-12-221-1/+191
| | | | | | | | | | | | | | | | - GPLL2, GPLL4 and GPLL6 are general PLL clocks and parent for all core peripherals. - UBI PLL is mainly used by NSS (Network Switching System). IPQ8074 has 2 instances of NSS UBI cores and UBI PLL will be used to control the core frequency. - NSS Crypto PLL is mainly used by NSS Crypto Engine which supports the multiple cryptographic algorithm used in Ethernet. - IPQ8074 frequency plan does not require change in PLL post dividers so marked the same as read-only. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: ipq8074: fix missing GPLL0 divider widthAbhishek Sahu2017-12-221-0/+1
| | | | | | | | GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: add parent map for regmap muxAbhishek Sahu2017-12-224-11/+18
| | | | | | | | | | | | | Currently the driver assumes the register configuration value is identical to its index in the parent map. This patch adds the parent map field in regmap mux clock node which contains the mapping of parent index with actual register configuration value. If regmap node contains this parent map then the configuration value will be taken from this parent map instead of simply writing the index value. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: add read-only divider operationsAbhishek Sahu2017-12-222-0/+30
| | | | | | | | | | | Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM dividers which is equivalent to generic divider operations in 'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: add read-only alpha pll post divider operationsAbhishek Sahu2017-12-142-0/+26
| | | | | | | | | | | Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM alpha pll post divider which is equivalent to generic divider operations in 'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support for 2 bit PLL post dividerAbhishek Sahu2017-12-141-4/+17
| | | | | | | | | Current PLL driver only supports 4 bit PLL post divider so modified the PLL divider operations to support 2 bit PLL post divider. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support Brammo type Alpha PLLAbhishek Sahu2017-12-142-0/+10
| | | | | | | | | The Brammo type of Alpha PLL doesn't allow configuration of a VCO, but it does support dynamic update in which the frequency can be changed dynamically without turning off the PLL. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support Huayra type Alpha PLLAbhishek Sahu2017-12-142-5/+189
| | | | | | | | | | | | | | The Huayra type Alpha PLL has a 16 bit alpha value, and depending on the alpha_mode, the alpha value can be treated as M/N value or as a two’s compliment number. This PLL supports dynamic programming. Since the decoding of alpha val and dynamic programming are completely different from other Alpha PLLs we add separate functions for Huayra PLLs. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support for dynamic updating the PLLAbhishek Sahu2017-12-142-4/+80
| | | | | | | | | | | | | | | | | | | | Some of the Alpha PLLs support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence: 1. Write the desired values to L_VAL and ALPHA_VAL registers 2. Toggle pll_latch_input from low to high 3. Wait for pll_ack_latch to transition from low to high The new L and alpha values have been latched. It may take some time for the PLL to fully settle with these new values. 4. Pull pll_latch_input low Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support for alpha mode configurationAbhishek Sahu2017-12-132-0/+8
| | | | | | | | | | | The current configuration does not fully configure PLL alpha mode and values so this patch 1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha. 2. Adds alpha enable and alpha mode configuration support. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: flag for 64 bit CONFIG_CTLAbhishek Sahu2017-12-131-1/+6
| | | | | | | | | | Some of the Alpha PLLs (like Spark and Brammo) don't have a CONFIG_CTL_U register. Add logic to detect when PLLs don't have this second config register and skip programming it during PLL initialization. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: fix 16 bit alpha support calculationAbhishek Sahu2017-12-132-25/+34
| | | | | | | | | | | | | | | | | | | The alpha value calculation has been written for 40-bit alpha values which doesn't work work properly for 16-bit ones. The alpha value is calculated on the basis of ALPHA_BITWIDTH to make the computation easy for 40 bit alpha. After calculating the 32 bit alpha, it is converted to 40 bit alpha by making lower bits zero. But if actual alpha register width is less than ALPHA_BITWIDTH, then the actual width can be used for calculation. This also means, during the 40 bit alpha pll set rate path, the lower alpha register is not configured Change the code to calculate the rate and register values from 'alpha_width' instead of hard-coding it so that it can work for the different widths that are supported. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: support for alpha pll propertiesAbhishek Sahu2017-12-136-62/+120
| | | | | | | | | | | | | | | | | | | | Alpha PLL is a generic name used for QCOM PLLs which uses L and Alpha values for configuring the integer and fractional part. QCOM SoCs use different types of Alpha PLLs for which basic software configuration part is common with following differences. 1. All these PLLs have the same basic registers like PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are different between PLLs types. 2. The dynamic programming sequence is different in some of the Alpha PLLs 3. Some of the PLLs don’t have 64 bit config control, 64 bit user control, VCO configuration, etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-11-18146-965/+6114
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
| * Merge branch 'clk-cleanup' into clk-nextStephen Boyd2017-11-1522-139/+92
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-cleanup: clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers clk: mmp: Use common error handling code in mmp_clk_register_mix() clk: mmp: Delete error messages for failed memory allocations clk: clk-xgene: Adjust six checks for null pointers clk: clk-xgene: Delete error messages for failed memory allocations clk: clk-u300: Fix a typo in two comment lines clk: clk-u300: Add some spaces for better code readability clk: clk-u300: Improve sizeof() usage clk: clk-u300: Delete error messages for failed memory allocations clk: clk-mux: Improve a size determination in clk_hw_register_mux_table() clk: clk-mux: Delete an error message for a failed memory allocation
| | * clk: kona-setup: Delete error messages for failed memory allocationsMarkus Elfring2017-11-141-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * ARC: clk: fix spelling mistake: "configurarion" -> "configuration"Colin Ian King2017-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | Trivial fix to spelling mistake in dev_dbg message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: cdce925: remove redundant check for non-null parent_nameColin Ian King2017-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check for a non-null parent_name is always true as there is an earlier check for a null parent_name that returns -ENODEV. Remove this redundant check and always set init.num_parents to 1. Detected by CoverityScan CID#1309477 ("Logically dead code") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: versatile: Improve sizeof() usageMarkus Elfring2017-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: versatile: Delete error messages for failed memory allocationsMarkus Elfring2017-11-141-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: ux500: Improve sizeof() usageMarkus Elfring2017-11-143-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the specification of data structures by pointer dereferences as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: ux500: Delete error messages for failed memory allocationsMarkus Elfring2017-11-143-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: spear: Delete error messages for failed memory allocationsMarkus Elfring2017-11-144-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: ti: Delete error messages for failed memory allocationsMarkus Elfring2017-11-142-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: mmp: Adjust checks for NULL pointersMarkus Elfring2017-11-144-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The script “checkpatch.pl” pointed information out like the following: Comparison to NULL could be written !... Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: mmp: Use common error handling code in mmp_clk_register_mix()Markus Elfring2017-11-141-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add a jump target so that a bit of exception handling can be better reused at the end of this function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: mmp: Delete error messages for failed memory allocationsMarkus Elfring2017-11-143-14/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-xgene: Adjust six checks for null pointersMarkus Elfring2017-11-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written ... Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-xgene: Delete error messages for failed memory allocationsMarkus Elfring2017-11-141-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-u300: Fix a typo in two comment linesMarkus Elfring2017-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | Add a missing character in these descriptions. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-u300: Add some spaces for better code readabilityMarkus Elfring2017-11-141-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | Use space characters at some source code places according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-u300: Improve sizeof() usageMarkus Elfring2017-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the specification of data structures by pointer dereferences as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-u300: Delete error messages for failed memory allocationsMarkus Elfring2017-11-141-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit extra messages for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-mux: Improve a size determination in clk_hw_register_mux_table()Markus Elfring2017-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: clk-mux: Delete an error message for a failed memory allocationMarkus Elfring2017-11-141-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [sboyd@codeaurora.org: Cleanup commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: stm32h7: fix test of clock configGabriel Fernandez2017-11-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | fix test of composite clock config (bad copy / past) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Fixes: 3e4d618b0722 ("clk: stm32h7: Add stm32h743 clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: pxa: fix building on older compilersArnd Bergmann2017-11-151-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc-4.4 got confused by the inline assembler statement: drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_core_turbo_switch': drivers/clk/pxa/clk-pxa.c:152: error: expected string literal before ')' token This removes the extraneous ':' to let all compilers parse the driver correctly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: sunxi-ng: a83t: Fix i2c buses bitsMylene JOSSERAND2017-11-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i2c1 and i2c2 bits for CCU are not bit 0 but bit 1 and bit 2. Because of that, the i2c0 (bit 0) was not correctly configured. Fixed the correct bits for i2c1 and i2c2. Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: ti: dra7-atl-clock: fix child-node lookupsJohan Hovold2017-11-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix child node-lookup during probe, which ended up searching the whole device tree depth-first starting at parent rather than just matching on its children. Note that the original premature free of the parent node has already been fixed separately, but that fix was apparently never backported to stable. Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Fixes: 660e15519399 ("clk: ti: dra7-atl-clock: Fix of_node reference counting") Cc: stable <stable@vger.kernel.org> # 3.16: 660e15519399 Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Johan Hovold <johan@kernel.org> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: qcom: common: fix legacy board-clock registrationJohan Hovold2017-11-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure to search only the child nodes of "/clocks", rather than the whole device-tree depth-first starting at "/clocks" when determining whether to register a fixed clock in the legacy board-clock registration helper. Fixes: ee15faffef11 ("clk: qcom: common: Add API to register board clocks backwards compatibly") Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | Merge branch 'clk-uniphier' into clk-nextStephen Boyd2017-11-142-5/+4
| |\ \ | | | | | | | | | | | | | | | | | | | | * clk-uniphier: clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data
| | * | clk: uniphier: fix DAPLL2 clock rate of Pro5Masahiro Yamada2017-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | clk: uniphier: fix parent of miodmac clock dataMasahiro Yamada2017-11-141-4/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | The "miodmac" is not a child of "stdmac". They are independent from each other. Fix it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | Merge branch 'clk-gpio' into clk-nextStephen Boyd2017-11-141-56/+28
| |\ \ | | | | | | | | | | | | | | | | | | | | * clk-gpio: clk: clk-gpio: Request GPIO descriptor as LOW clk: clk-gpio: Make GPIO clock provider use descriptors only
| | * | clk: clk-gpio: Request GPIO descriptor as LOWLinus Walleij2017-11-021-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Requesting the GPIOD_OUT_LOW low will make sure the GPIO is deasserted when requested. The gpiolib core will make sure that if the GPIO line is active low, it will be logically driven high when deasserted, see drivers/gpiolib.c gpiod_configure_flags(). Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-13 13:13:57 +0100