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| | | | * | | clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as criticalAngeloGioacchino Del Regno2021-02-141-0/+1
| | | | * | | clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as criticalAngeloGioacchino Del Regno2021-02-141-0/+6
| | | | * | | clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate settingAngeloGioacchino Del Regno2021-02-141-1/+9
| | | | * | | clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdscAngeloGioacchino Del Regno2021-02-141-2/+6
| | | | * | | clk: qcom: gdsc: Implement NO_RET_PERIPH flagAngeloGioacchino Del Regno2021-02-142-3/+10
| | | | * | | clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always onAngeloGioacchino Del Regno2021-02-081-1/+1
| | | | * | | clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clksAngeloGioacchino Del Regno2021-02-081-0/+10
| | | | * | | clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno2021-02-081-50/+50
| | | | * | | clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as criticalAngeloGioacchino Del Regno2021-02-081-0/+6
| | | | * | | clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clockAngeloGioacchino Del Regno2021-02-081-0/+20
| | | | * | | clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clockAngeloGioacchino Del Regno2021-02-081-0/+17
| | | | * | | clk: qcom: videocc: Add gdsc mmcx-reg supply hookBryan O'Donoghue2021-02-081-0/+4
| | | | * | | clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_CLKBryan O'Donoghue2021-02-081-0/+19
| | | | * | | clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_DIV_CLK_SRCBryan O'Donoghue2021-02-081-0/+16
| | | | * | | clk: qcom: gcc: Add clock driver for SM8350Vivek Aknurwar2021-02-083-0/+3799
| | | | * | | clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLLVivek Aknurwar2021-02-082-0/+177
| | | | * | | clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()Vinod Koul2021-02-081-7/+11
| | | | * | | clk: qcom: clk-alpha-pll: replace regval with valVinod Koul2021-02-081-10/+10
| | | | * | | clk: qcom: gcc: Add global clock controller driver for SC8180xBjorn Andersson2021-02-083-0/+4639
| | | | * | | clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ONTaniya Das2021-02-081-43/+4
| | | | * | | clk: qcom: rpmhcc: Add sc8180x rpmh clocksBjorn Andersson2021-02-081-0/+25
| | | | * | | clk: qcom: gfm-mux: fix clk maskSrinivas Kandagatla2021-02-081-4/+4
| | | | * | | clk: qcom: Add SDX55 APCS clock controller supportManivannan Sadhasivam2021-02-083-0/+159
| | | | * | | clk: qcom: Add A7 PLL supportManivannan Sadhasivam2021-02-083-0/+109
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| | | * | | clk: mstar: msc313-mpll: Fix format specifierDaniel Palmer2021-02-161-1/+1
| | | * | | clk: mstar: Allow MStar clk drivers to be compile testedDaniel Palmer2021-02-162-3/+7
| | | * | | clk: mstar: MStar/SigmaStar MPLL driverDaniel Palmer2021-02-145-0/+168
| | | * | | clk: fixed: add devm helper for clk_hw_register_fixed_factor()Daniel Palmer2021-02-141-6/+33
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| | * / / clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen2021-02-124-3/+238
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| *-------. \ \ Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-ro...Stephen Boyd2021-02-165-38/+153
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| | | | | | * | | clk: BD718x7: Do not depend on parent driver dataMatti Vaittinen2021-02-121-5/+7
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| | | | | * / / clk: qoriq: use macros to generate pll_maskWasim Khan2021-02-141-19/+43
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| | | | * / / clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen2021-02-111-10/+27
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| | | * / / clk: si570: Skip NVM to RAM recall operation if an optional property is setSaeed Nowshadi2021-02-111-4/+12
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| | * / / clk: vc5: Add support for optional load capacitanceAdam Ford2021-02-111-0/+64
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| *-----. \ \ Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into c...Stephen Boyd2021-02-1623-162/+156
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| | | | | * | | clk: at91: Fix the declaration of the clocksTudor Ambarus2021-02-109-28/+28
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| | | | * | | clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2021-02-092-4/+0
| | | | * | | clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl2021-01-041-40/+5
| | | | * | | clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl2021-01-041-2/+3
| | | | * | | clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl2021-01-041-1/+2
| | | | * | | clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl2021-01-041-1/+1
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| | | * | | clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible headerLee Jones2021-01-301-0/+1
| | | * | | clk: imx8mn: add clkout1/2 supportLucas Stach2021-01-301-0/+12
| | | * | | clk: imx8mm: add clkout1/2 supportLucas Stach2021-01-301-0/+12
| | | * | | clk: imx8mq: add PLL monitor outputLucas Stach2021-01-301-0/+22
| | | * | | clk: imx: clk-imx31: Remove unused static const table 'uart_clks'Lee Jones2021-01-291-10/+0
| | | * | | clk: imx6q: demote warning about pre-boot ldb_di_clk reparentingAhmad Fatoum2021-01-291-3/+3
| | | * | | clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystemsLiu Ying2021-01-051-0/+10
| | | * | | clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()Liu Ying2021-01-051-2/+10
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