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| | | * | clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_r...Cai Huoqing2021-09-131-3/+1
| | | * | clk: sunxi-ng: Use a separate lock for each CCU instanceSamuel Holland2021-09-131-4/+5
| | | * | clk: sunxi-ng: Prevent unbinding CCUs via sysfsSamuel Holland2021-09-138-0/+8
| | | * | clk: sunxi-ng: Unregister clocks/resets when unbindingSamuel Holland2021-09-1323-41/+100
| | | * | clk: sunxi-ng: Add machine dependency to A83T CCUSamuel Holland2021-09-131-0/+1
| | | * | clk: sunxi-ng: mux: Remove unused 'reg' fieldSamuel Holland2021-09-131-1/+0
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| | * | clk: composite: Use rate_ops.determine_rate when also a mux is availableMartin Blumenstingl2021-10-181-20/+48
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| *---. \ \ Merge branches 'clk-imx', 'clk-ux500' and 'clk-debugfs' into clk-nextStephen Boyd2021-11-0216-362/+1113
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| | | | * | | clk: use clk_core_get_rate_recalc() in clk_rate_get()Claudiu Beznea2021-10-271-1/+4
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| | | * / | clk: ux500: Add driver for the reset portions of PRCCLinus Walleij2021-10-275-13/+243
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| | * | | clk: imx: Make CLK_IMX8ULP select MXC_CLKFabio Estevam2021-10-061-0/+1
| | * | | clk: imx: imx6ul: Fix csi clk gate registerStefan Riedmueller2021-10-011-1/+6
| | * | | clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller2021-10-011-1/+1
| | * | | clk: imx: Fix the build break when clk-imx8ulp build as moduleJacky Bai2021-10-013-0/+3
| | * | | clk: imx: Add the pcc reset controller support on imx8ulpJacky Bai2021-09-302-3/+123
| | * | | clk: imx: Add clock driver for imx8ulpJacky Bai2021-09-303-0/+467
| | * | | clk: imx: Update the pfdv2 for 8ulp specific supportJacky Bai2021-09-303-13/+21
| | * | | clk: imx: disable the pfd when set pfdv2 clock rateJacky Bai2021-09-301-2/+11
| | * | | clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulpJacky Bai2021-09-301-1/+1
| | * | | clk: imx: disable i.mx7ulp composite clock during initializationAnson Huang2021-09-301-0/+14
| | * | | clk: imx: Update the compsite driver to support imx8ulpJacky Bai2021-09-302-3/+64
| | * | | clk: imx: Update the pllv4 to support imx8ulpJacky Bai2021-09-303-13/+34
| | * | | clk: imx: Rework imx_clk_hw_pll14xx wrapperAbel Vesa2021-09-301-7/+3
| | * | | clk: imx: Rework all imx_clk_hw_composite wrappersAbel Vesa2021-09-302-32/+36
| | * | | clk: imx: Rework all clk_hw_register_divider wrappersAbel Vesa2021-09-301-18/+11
| | * | | clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa2021-09-301-46/+22
| | * | | clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa2021-09-301-51/+26
| | * | | clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa2021-09-171-41/+23
| | * | | clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa2021-09-171-20/+6
| | * | | clk: imx: Remove unused helpersAbel Vesa2021-09-171-103/+0
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| *-----. \ \ Merge branches 'clk-leak', 'clk-rockchip', 'clk-renesas' and 'clk-at91' into ...Stephen Boyd2021-11-0237-412/+1543
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| | | | | * | | clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea2021-10-271-1/+1
| | | | | * | | clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea2021-10-271-10/+1
| | | | | * | | clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-2713-82/+186
| | | | | * | | clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea2021-10-274-29/+95
| | | | | * | | clk: at91: clk-master: fix prescaler logicClaudiu Beznea2021-10-271-1/+1
| | | | | * | | clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea2021-10-271-2/+5
| | | | | * | | clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea2021-10-271-2/+2
| | | | | * | | clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea2021-10-271-2/+2
| | | | | * | | clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea2021-10-271-2/+3
| | | | | * | | clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea2021-10-271-3/+3
| | | | | * | | clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea2021-10-271-27/+23
| | | | | * | | clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea2021-10-271-0/+1
| | | | | * | | clk: at91: pmc: execute suspend/resume only for backup modeClaudiu Beznea2021-10-271-0/+39
| | | | | * | | clk: at91: re-factor clocks suspend/resumeClaudiu Beznea2021-10-2712-181/+558
| | | | | * | | clk: at91: check pmc node status before registering syscore opsClément Léger2021-10-081-0/+5
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| | | | * | | clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov2021-10-153-0/+3
| | | | * | | clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das2021-10-082-0/+40
| | | | * | | clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das2021-10-082-0/+130
| | | | * | | clk: renesas: r8a779a0: Add RPC supportWolfram Sang2021-10-081-0/+32
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